Semiconductor device having SOI structure

Claim 2

A semiconductor device comprising: an SOI substrate including a semiconductor substrate, an insulating layer formed on the semiconductor substrate and an SOI layer formed on the insulating layer; a transistor formed on the SOI layer and including (a) a first source/drain region formed in the SOI layer, (b) a gate electrode formed on the SOI layer with a gate insulation film interposed therebetween, and (c) a second source/drain region formed in the SOI layer; and a conductive layer extending above the gate electrode and in electrical contact with the first source/drain region, wherein each of the gate electrode and the conductive layer has an etched side surface in a single plane extending in a substantially perpendicular direction above the transistor in proximity to an edge of the second source/drain region.

Claim 3

The semiconductor device according to claim 1, wherein the etched side surfaces of the gate electrode and the conductive layer are etched in the same etching step.

Claim 4

The semiconductor device according to claim 1, comprising a DRAM.

Claim 5

The semiconductor device according to claim 3, wherein the transistor is a memory cell transistor.

Claim 6

The semiconductor device according to claim 3, comprising a peripheral circuit, wherein the transistor is a peripheral circuit transistor.

Claim 7

The semiconductor device according to claim 1, wherein the transistor is a stack type memory cell transistor.

Claim 8

The semiconductor device according to claim 6, wherein the conductive layer is a storage node of a capacitor formed under a bit line.

Claim 9

The semiconductor device according to claim 6, wherein the conductive layer is a bit line formed under a storage node of a capacitor.

Claim 10

The semiconductor device according to claim 1, wherein the transistor is a trench type memory cell transistor.

Claim 11

The semiconductor device according to claim 5, wherein the peripheral circuit comprises a logic inverter.

Claim 12

The semiconductor device according to claim 1, wherein the first source/drain region is formed before the second source/drain region.

Claim 13

A dynamic random access memory comprising: an SOI substrate including a semiconductor substrate, an insulating layer formed on the semiconductor substrate and an SOI layer formed on the insulating layer; a transistor formed on the SOI layer and including (a) a first source/drain region formed in the SOI layer, (b) a gate electrode formed on the SOI layer with a gate insulation film interposed therebetween, and (c) a second source/drain region formed in the SOI layer; a pad to be connected to a bit line, said pad extending above the gate electrode and being in electrical contact with the first source/drain region, wherein each of the gate electrode and the pad has an etched side surface in a single plane extending in a substantially perpendicular direction above the transistor in proximity to an edge of the second source/drain region; and a storage node in electrical contact with the second source/drain region.

Claim 14

A dynamic random access memory comprising: an SOI substrate including a semiconductor substrate, an insulating layer formed on the semiconductor substrate and an SOI layer formed on the insulating layer; a transistor formed on the SOI layer and including (a) a first source/drain region formed in the SOI layer, (b) a gate electrode formed on the SOI layer with a gate insulation film interposed therebetween, and (c) a second source/drain region formed in the SOI layer; a pad to be connected to a bit line, said pad extending above the gate electrode and being in electrical contact with the first source/drain region, wherein each of the gate electrode and the pad has an etched side surface in a single plane extending in a substantially perpendicular direction above the transistor in proximity to an edge of the second source/drain region; and a storage node in electrical contact with the second source/drain region.

Claim 15

The dynamic random access memory according to claim 12, wherein the storage node is located at the higher position than the pad to be connected to the bit line.

Claim 16

The dynamic random access memory according to claim 12, wherein the storage node is formed in a trench formed in the SOI substrate.