DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor

Claim 2

An integrated circuit including an array of memory cells, comprising: (a) a monocrystalline substrate, (b) a field oxide formed on said substrate defining plural locations for memory cells in said array of memory cells, (c) each memory cell having: (i) a pair of spaced implanted regions disposed in said substrate, (ii) a gate electrode spaced from said substrate, (iii) a first capacitor electrode on said substrate contacting one of said implanted regions and extending over at least a portion of and spaced from said gate electrode and over a portion of said field oxide, (d) a second capacitor electrode coextensive over said array, in every memory cell said second capacitor electrode extending substantially over said gate electrode and said first capacitor electrode and being spaced therefrom and extending over said field oxide beyond said first capacitor electrode, and (e) a bit line extending over the second capacitor electrode and having a portion extending down to the substrate and contacting the other one of said implanted regions.

Claim 3

A circuit as set forth in claim 1 further including a dielectric layer between said substrate and said gate electrode.

Claim 4

A circuit as set forth in claim 2 wherein said gate electrode is formed from polysilicon.

Claim 5

A circuit as set forth in claim 2 wherein said first and second capacitor electrodes are formed from polysilicon.

Claim 6

A circuit as set forth in claim 3 wherein said first and second capacitor electrodes are formed from polysilicon.

Claim 7

A circuit as set forth in claim 1 further including a dielectric stack extending over said first capacitor electrode formed of a layer of silicon oxide, a region of silicon nitride thereover and then a layer of silicon oxide.

Claim 8

A circuit as set forth in claim 5 further including a dielectric stack extending over said first capacitor electrode formed of a layer of silicon oxide, a region of silicon nitride thereover and then a layer of silicon oxide.

Claim 9

A circuit as set forth in claim 1 wherein said gate electrode extends over both said implanted regions.

Claim 10

A circuit as set forth in claim 1 further including a dielectric layer between said first and second capacitor electrodes.

Claim 11

A circuit as set forth in claim 9 wherein said dielectric includes at least layers of different materials.

Claim 12

A circuit as set forth in claim 10 wherein at least one of said layers is an oxide.

Claim 13

A circuit as set forth in claim 10 wherein at least one of said layers is a nitride.

Claim 14

A circuit as set forth in claim 11 wherein at least one of said layers is nitride.

Claim 15

A circuit as set forth in claim 1 in which said bit line is made of metal, there is a slot over the other one of said implanted regions cutting through at least said second capacitor electrode and extending down to the other one of said implanted regions, and said bit line extending down to the other one of said implanted regions through said slot.

Claim 16

A circuit as set forth in claim 1 in which said second capacitor electrode is coextensive over said array except where interrupted by a contact slot arranged over the other one of said implanted regions.

Claim 17

A circuit as set forth in claim 1 in which said gate electrode is formed in first level polysilicon, said first capacitor electrode is formed in second level polysilicon and said second capacitor is formed in third level polysilicon.

Claim 18

A circuit as set forth in claim 1 in which the other one of said implant regions is common with a second memory cell and said bit line portion extends down to the substrate between the first capacitor electrodes of each memory cell.

Claim 19

A circuit as set forth in claim 1 in which said second capacitor electrode extends around at least part of the side of said first capacitor electrode at the location where said second capacitor electrode extends over the field oxide beyond said first capacitor electrode.

Claim 20

An integrated circuit including an array of dynamic random access memory cells, comprising: (a) a monocrystalline substrate; (b) a field oxide formed on said substrate defining plural locations for pairs of memory cells in said array of memory cells; (c) each location providing two dynamic random access memory cells with each cell providing one transistor and one capacitor, each location having: (i) three spaced implant regions disposed in said substrate to form a central implant region and two opposed lateral implant regions, each cell containing one lateral implant region and said two cells sharing said central implant region, the implant regions forming the sources and the drains of the transistors, (ii) two gate electrodes spaced above said substrate, each gate electrode being arranged between said central implant region and one of said lateral implant regions, said gate electrodes forming the gates of the transistors, (iii) a pair of first capacitor electrodes on said substrate, each first capacitor electrode contacting one of said lateral implanted regions, each first capacitor electrode extending over at least a portion of and being spaced from one of said gate electrodes and having a side extending over a portion of said field oxide, each cell including one of said first capacitor electrodes and each of said first capacitor electrodes forming a part of said capacitors, and (iv) a pair of dielectric layers, one over each of said first capacitor electrodes including the sides of the first capacitor electrodes, each of said dielectric layers forming a part of said capacitors; (d) a second capacitor electrode coextensive over said array, in every memory cell said second capacitor electrode extending substantially over and being spaced from one of said gate electrodes, being over said first capacitor electrode and extending over said field oxide beyond said first capacitor electrode, said second capacitor electrode extending around at least part of the sides of every first capacitor electrode, said second capacitor electrode having an opening over the central implanted region and the opening extending down to the central implanted region, the second capacitor electrode forming a part of every capacitor in every memory cell; and (e) at least one bit line extending over and being spaced from the second capacitor electrode, said bit line having a portion extending down to the substrate and contacting said central implanted region through the opening in the second capacitor electrode.

Claim 21

An integrated circuit including an array of dynamic random access memory cells, comprising: (a) a monocrystalline substrate; (b) a field oxide formed on said substrate defining plural locations for pairs of memory cells in said array of memory cells; (c) each location providing two dynamic random access memory cells with each cell providing one transistor and one capacitor, each location having: (i) three spaced implant regions disposed in said substrate to form a central implant region and two opposed lateral implant regions, each cell containing one lateral implant region and said two cells sharing said central implant region, the implant regions forming the sources and the drains of the transistors, (ii) two gate electrodes spaced above said substrate, each gate electrode being arranged between said central implant region and one of said lateral implant regions, said gate electrodes forming the gates of the transistors, (iii) a pair of first capacitor electrodes on said substrate, each first capacitor electrode contacting one of said lateral implanted regions, each first capacitor electrode extending over at least a portion of and being spaced from one of said gate electrodes and having a side extending over a portion of said field oxide, each cell including one of said first capacitor electrodes and each of said first capacitor electrodes forming a part of said capacitors, and (iv) a pair of dielectric layers, one over each of said first capacitor electrodes including the sides of the first capacitor electrodes, each of said dielectric layers forming a part of said capacitors; (d) a second capacitor electrode coextensive over said array, in every memory cell said second capacitor electrode extending substantially over and being spaced from one of said gate electrodes, being over said first capacitor electrode and extending over said field oxide beyond said first capacitor electrode, said second capacitor electrode extending around at least part of the sides of every first capacitor electrode, said second capacitor electrode having an opening over the central implanted region and the opening extending down to the central implanted region, the second capacitor electrode forming a part of every capacitor in every memory cell; and (e) at least one bit line extending over and being spaced from the second capacitor electrode, said bit line having a portion extending down to the substrate and contacting said central implanted region through the opening in the second capacitor electrode.