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US5381365A Expired / Lapsed US ⏱️ 0.0 years remaining

Dynamic random access memory having stacked type capacitor and manufacturing method therefor

Assignee: Renesas Electronics Corp
•
Filing: 1993-06-30
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Granted: 1995-01-10
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Expires: 2013-06-30
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Abstract

Abstract The DRAM according to the present invention comprises so-called cylindrical stacked type capacitors. Each of the cylindrical stacked type capacitors comprises a base portion extending flat on an insulation layer and a surface of a substrate, and a cylindrical portion extending vertically and upwardly from the base portion. Then, the cylindrical portion vertically and upwardly protrudes from an outermost peripheral position of the base portion. As a result, an area where electrodes of the capacitor and capacitance of the capacitor can be increased. Furthermore, with a bit line located below an electrode layer of the capacitor, adjacent capacitors above the bit line can be isolated. Accordingly, it is possible to prevent the bit line contact from defining an isolation distance between the capacitors. Furthermore, an isolating layer patterned by etching is used as an isolating region between the capacitors and a lower electrode of the capacitor is formed along a surface of the isolating layer to form an isolation region between the adjacent capacitors. In addition, the lower electrode of the cylindrical stacked type capacitor is integrally formed by using a step formed in the insulation layer. As a result, the manufacturing step is simplified.

Inventors

  • 👤 Natsuo Ajika
  • 👤 Hideaki Arima
  • 👤 Atsushi Hachisuka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 22:23
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 134 words
A DRAM comprising: a semiconductor substrate of a second conductivity type having a main surface and an impurity region of a first conductivity type on the main surface, an insulation layer formed on the main surface of said semiconductor substrate and having an opening portion exposing said impurity region, said insulation layer having an upper surface substantially parallel to the main surface of said substrate, a first electrode layer including a first portion formed on and in contact with a surface of said impurity region and said upper surface of said insulation layer, and a second portion having a frusto-conical shape and extending vertically from said upper surface of said insulation layer, a dielectric layer covering a surface of said first electrode layer, a second electrode layer covering a surface of said dielectric layer.
Claim 2
Dependent Claim 134 words
A DRAM comprising: a semiconductor substrate of a second conductivity type having a main surface and an impurity region of a first conductivity type on the main surface, an insulation layer formed on the main surface of said semiconductor substrate and having an opening portion exposing said impurity region, said insulation layer having an upper surface substantially parallel to the main surface of said substrate, a first electrode layer including a first portion formed on and in contact with a surface of said impurity region and said upper surface of said insulation layer, and a second portion having a frusto-conical shape and extending vertically from said upper surface of said insulation layer, a dielectric layer covering a surface of said first electrode layer, a second electrode layer covering a surface of said dielectric layer.
Claim 3
Dependent Claim 24 words
A DRAM as recited in claim 1, wherein said second portion having a frusto-conical shape extends along an outermost periphery of said first portion.
Claim 4
Dependent Claim 128 words
A DRAM comprising: a semiconductor substrate of a second conductivity type having a main surface and an impurity region of a first conductivity type on the main surface, an insulation layer formed on the main surface of said semiconductor substrate and having an opening portion exposing said impurity region, a first electrode layer including a first portion formed on and in contact with a surface of said impurity region and a surface of salad insulation layer, and a second portion having a frusto-conical shape and extending vertically with respect to said main surface of said semiconductor substrate and along an outermost periphery of said first portion, a dielectric layer covering a surface of said first electrode layer, a second electrode layer covering a surface of said dielectric layer.
Claim 5
Dependent Claim 128 words
A DRAM comprising: a semiconductor substrate of a second conductivity type having a main surface and an impurity region of a first conductivity type on the main surface, an insulation layer formed on the main surface of said semiconductor substrate and having an opening portion exposing said impurity region, a first electrode layer including a first portion formed on and in contact with a surface of said impurity region and a surface of salad insulation layer, and a second portion having a frusto-conical shape and extending vertically with respect to said main surface of said semiconductor substrate and along an outermost periphery of said first portion, a dielectric layer covering a surface of said first electrode layer, a second electrode layer covering a surface of said dielectric layer.
Claim 6
Dependent Claim 33 words
A DRAM as recited in claim 3, wherein said second portion having a frusto-conical shape has an outer surface which converges in a direction away from said main surface of said semiconductor substrate.
Claim 7
Dependent Claim 33 words
A DRAM as recited in claim 3, wherein said second portion having a frusto-conical shape has an outer surface which diverges in a direction away from said main surface of said semiconductor substrate.

References Cited (Backward Citations)

JPS602784A Cited
JPS62128168A Cited
JPH01257365A Cited
DE3918924A1 Cited
US5047817A Cited
DE3922456A1 Cited
US5101251A Cited
DE4113233A1 Cited
US5218219A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-01-09 1998-07-11 1999-01-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-01-09 2002-07-11 2003-01-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-01-09 2006-07-11 2007-01-10 $7700.00 Window Closed / Lapsed

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