US5218219A
Expired / Lapsed
US
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Semiconductor memory device having a peripheral wall at the boundary region of a memory cell array region and a peripheral circuit region
Assignee: Mitsubishi Electric Corp
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Filing: 1991-04-04
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Granted: 1993-06-08
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Expires: 2011-04-04
Abstract
Abstract A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.
Inventors
- 👤 Natsuo Ajika
- 👤 Hideaki Arima
- 👤 Kaoru Motonami
- 👤 Atsushi Hachisuka
- 👤 Tomonori Okudaira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:06
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10B12/01; H10B12/02; H10B12/03
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
292 words
A semiconductor memory device formed on a semiconductor substrate having at least one memory cell array region and a peripheral circuit region, said semiconductor substrate having an upper surface, comprising: a plurality of memory cells formed on said memory cell array region on said semiconductor substrate, each said memory cell including a transistor having a pair of impurity regions formed at said upper surface of said semiconductor substrate and a gate electrode, and a capacitor connected to one impurity region of said transistor, said capacitor having a first electrode of generally U shaped cross section, said first electrode having a first bottom portion extending generally parallel to said upper surface of said semiconductor substrate and at least one projecting side portion extending substantially perpendicular to and above said first bottom portion so as to form the bottom and sides of generally U shaped cross section, and a second electrode insulated from said first electrode by a dielectric film, a plurality of transistors for peripheral circuits formed on the peripheral circuit region of said semiconductor substrate, and a conductor of generally U shaped cross section, said conductor having a first bottom portion extending generally parallel to said upper surface of said semiconductor substrate and at least one projecting side portion extending substantially perpendicular to and above said first bottom portion so as to form the bottom and sides of generally U shaped cross section, said conductor enclosing plural memory cells of said memory cell array region, wherein the end of said projecting side portion of said conductor most remote from said upper surface of said substrate is substantially coplanar with the end of said projecting side portion most remote from said upper surface of said substrate of said first electrode of said capacitor.
Claim 2
Dependent Claim
292 words
A semiconductor memory device formed on a semiconductor substrate having at least one memory cell array region and a peripheral circuit region, said semiconductor substrate having an upper surface, comprising: a plurality of memory cells formed on said memory cell array region on said semiconductor substrate, each said memory cell including a transistor having a pair of impurity regions formed at said upper surface of said semiconductor substrate and a gate electrode, and a capacitor connected to one impurity region of said transistor, said capacitor having a first electrode of generally U shaped cross section, said first electrode having a first bottom portion extending generally parallel to said upper surface of said semiconductor substrate and at least one projecting side portion extending substantially perpendicular to and above said first bottom portion so as to form the bottom and sides of generally U shaped cross section, and a second electrode insulated from said first electrode by a dielectric film, a plurality of transistors for peripheral circuits formed on the peripheral circuit region of said semiconductor substrate, and a conductor of generally U shaped cross section, said conductor having a first bottom portion extending generally parallel to said upper surface of said semiconductor substrate and at least one projecting side portion extending substantially perpendicular to and above said first bottom portion so as to form the bottom and sides of generally U shaped cross section, said conductor enclosing plural memory cells of said memory cell array region, wherein the end of said projecting side portion of said conductor most remote from said upper surface of said substrate is substantially coplanar with the end of said projecting side portion most remote from said upper surface of said substrate of said first electrode of said capacitor.
Claim 3
Dependent Claim
23 words
The semiconductor memory device according to claim 1, wherein said conductor is formed to enclose the periphery of said memory cell array region.
Claim 4
Dependent Claim
36 words
The semiconductor memory device according to claim 1, including a device isolation layer for isolating said memory cell array region from said peripheral circuit region, and wherein said conductor is formed above said device isolation layer.
Claim 5
Dependent Claim
46 words
The semiconductor memory device according to claim 1, including a device isolation layer for isolating said memory cell array region from said peripheral circuit region, and said device isolation layer further includes an impurity region therein, wherein said conductor is electrically connected to said impurity region.
Claim 6
Dependent Claim
40 words
The semiconductor memory device according to claim 4, wherein said conductor is connected electrically to said impurity region through a pad; and said pad is comprised of a material identical to the material forming said first electrode of said capacitor.
Claim 7
Dependent Claim
41 words
The semiconductor memory device according to claim 3, wherein said conductor is formed on said device isolation region separated by a pad; and said pad is comprised of a material identical to the material forming said first electrode of said capacitor.
Claim 8
Dependent Claim
67 words
The semiconductor memory device according to claim 1, wherein said at least one projecting side portion of said conductor has a further portion adjacent the end of said projecting side portion of said conductor remote from said upper surface of said substrate, said further portion extending from said at least one projecting side portion of said conductor generally parallel to said upper surface of said semiconductor substrate.
Claim 9
Dependent Claim
37 words
The semiconductor memory device according to claim 7, wherein said further portion and said projecting side portion of said conductor form the shape of an inverted "L", and said further portion projects toward said peripheral circuit region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-07 | 1996-12-07 | 1997-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-07 | 2000-12-07 | 2001-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-07 | 2004-12-07 | 2005-06-08 | $7700.00 | Window Closed / Lapsed |