US5453633A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory device and a manufacturing method thereof
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-08-01
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Granted: 1995-09-26
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Expires: 2014-08-01
Abstract
Abstract Disclosed is a dynamic random access memory device (DRAM) having an increased cell capacitance and simplified manufacturing method thereof. The storage electrode the capacitor of the DRAM is connected to a semiconductor substrate through an opening formed in an insulating layer, and has a structure having an outer peripheral wall portion with a laterally extending bottom on the insulating layer and an inner central pillar portion including a hole of a certain depth within the opening in the center of the outer peripheral wall portion. Thus, cell capacitance is greatly increased within a limited unit cell area, its reliability is enhanced, and the manufacturing process is distinctly simplified.
Inventors
- 👤 Joo-young Yun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:15
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10B12/30; H10B12/31; H10B12/318; H10D1/043; H10D1/60; H10D1/68; H10D1/692; H10D1/696; H10D1/711; H10D1/716
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
153 words
A semiconductor memory device having a capacitor, comprising: (a) a semiconductor substrate having at least one transistor with a source region formed thereon; (b) an insulating layer formed over said substrate having said at least one transistor thereon, said insulating layer having an opening therethrough exposing said source region of said at least one transistor; (c) a capacitor storage electrode comprising: (1) an central pillar portion extending through said opening in said insulating layer and electrically connected to said source region, said central pillar portion having a longitudinal bore therein which extends downwardly towards said source region; and (2) a bottom portion extending outwardly from said central pillar portion at a point along said central pillar portion on or above an upper surface of said insulating layer; (d) a dielectric film formed over said storage electrode; and (e) a plate electrode formed over said dielectric film and electrically insulated from said storage electrode.
Claim 2
Dependent Claim
153 words
A semiconductor memory device having a capacitor, comprising: (a) a semiconductor substrate having at least one transistor with a source region formed thereon; (b) an insulating layer formed over said substrate having said at least one transistor thereon, said insulating layer having an opening therethrough exposing said source region of said at least one transistor; (c) a capacitor storage electrode comprising: (1) an central pillar portion extending through said opening in said insulating layer and electrically connected to said source region, said central pillar portion having a longitudinal bore therein which extends downwardly towards said source region; and (2) a bottom portion extending outwardly from said central pillar portion at a point along said central pillar portion on or above an upper surface of said insulating layer; (d) a dielectric film formed over said storage electrode; and (e) a plate electrode formed over said dielectric film and electrically insulated from said storage electrode.
Claim 3
Dependent Claim
28 words
A semiconductor memory device as claimed in claim 1, wherein a lower surface of said bottom portion of said storage electrode is spaced away from said insulating layer.
Claim 4
Dependent Claim
25 words
A semiconductor memory device as claimed in claim 2, wherein said dielectric film covers said lower surface of said bottom portion of said storage electrode.
Claim 5
Dependent Claim
16 words
A semiconductor memory device as claimed in claim 1, wherein said insulating layer is an oxide.
Claim 6
Dependent Claim
26 words
A semiconductor memory device as claimed in claim 1, wherein said insulating layer is a compound layer comprising an oxide layer and a silicon nitride layer.
Claim 7
Dependent Claim
19 words
A semiconductor memory device as claimed in claim 1, wherein said storage electrode is made from a polycrystalline silicon.
Claim 8
Dependent Claim
26 words
A semiconductor memory device as claimed in claim 1, wherein said bottom portion of said storage electrode is between about 500 Å and 1000 Å thick.
Claim 9
Dependent Claim
41 words
A semiconductor memory device as claimed in claim 1, wherein said capacitor storage electrode further includes a peripheral wall portion extending substantially perpendicularly from said bottom portion and parallel to said central pillar portion in a direction opposite said source region.
Claim 10
Dependent Claim
26 words
A semiconductor-memory device as claimed in claim 1, wherein said longitudinal bore in said central pillar portion extends towards said source region past said bottom portion.
Claim 11
Dependent Claim
28 words
A semiconductor memory device as claimed in claim 8, wherein said outer peripheral wall portion of said storage electrode is between about 500 Å and 1000 Å thick.
Claim 12
Dependent Claim
20 words
A semiconductor memory device as claimed in claim 1, wherein said bottom portion is spaced away from said insulating layer.
References Cited (Backward Citations)
US5164337A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-25 | 1999-03-27 | 1999-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-25 | 2003-03-27 | 2003-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-25 | 2007-03-27 | 2007-09-26 | $7700.00 | Window Closed / Lapsed |