Dynamic multiplexer circuits, systems, and methods having three signal inversions from input to output

Claim 2

A dynamic multiplexer circuit, comprising: an integer number N of data providing circuits, wherein the integer number N is greater than one and wherein each of the plurality of data providing circuits comprises: a precharge node to be precharged to a precharge voltage during a precharge phase; a conditional series discharge path connected to the precharge node and operable in response to at least one enabling input signal to discharge the precharge voltage at the precharge node during an evaluate phase thereby providing a first monotonic transitioning data signal at the precharge node; an inverter coupled to the precharge node and having an output for providing a second monotonic transitioning data signal, wherein the second monotonic transitioning data signal is complementary of the first monotonic transitioning data signal; the integer number N of data select paths, wherein each of the data select paths comprises a select transistor, the select transistor having a source coupled to receive the second monotonic transitioning data signal and a gate connected to receive a select signal; an output precharge node, wherein a drain of the select transistor in each of the data select paths is coupled to conditionally discharge the output precharge node; an output inverter having an input connected to the output precharge node; and wherein in a given evaluate phase of operation, in response to assertion of a select signal corresponding to one of the data select paths, the select transistor receiving the asserted select signal at its gate and the second monotonic transitioning data signal at its source conducts for providing an output data signal at an output of the output inverter, wherein the output data signal represents three signal inversions of the at least one enabling input signal.

Claim 3

The dynamic multiplexer circuit of claim 1, wherein the conditional series discharge path of each of the integer number N of data providing circuits consists of n-channel transistors.

Claim 4

The dynamic multiplexer circuit of claim 2 wherein the select transistor of each of the integer number N of data select paths is a p-channel transistor.

Claim 5

The dynamic multiplexer circuit of claim 3 wherein the precharge voltage comprises a first precharge voltage, and further comprising an n-channel precharge transistor connected to the output precharge node for precharging the output precharge node to a second precharge voltage during the precharge phase, wherein the second precharge voltage is lower than the first precharge voltage.

Claim 6

The dynamic multiplexer circuit of claim 1, wherein the conditional series discharge path of each of the integer number N of data providing circuits consists of p-channel transistors.

Claim 7

The dynamic multiplexer circuit of claim 5 wherein the select transistor of each of the integer number N of data select paths is an n-channel transistor.

Claim 8

The dynamic multiplexer circuit of claim 6 wherein the precharge voltage comprises a first precharge voltage, and further comprising a p-channel precharge transistor connected to the output precharge node for precharging the output precharge node to a second precharge voltage during the precharge phase, wherein the second precharge voltage is higher than the first precharge voltage.

Claim 9

The dynamic multiplexer circuit of claim 1: wherein the inverter for each of the integer number N of data providing circuits has an input and an output, and comprises: a first p-channel transistor having a source connected to a first voltage potential, a gate connected to the input of the inverter, and a drain connected to the output of the inverter; and a first n-channel transistor having a source connected to a second voltage potential lower than the first voltage potential, a gate connected to the input of the inverter, and a drain connected to the output of the inverter.

Claim 10

The dynamic multiplexer circuit of claim 8: wherein the first p-channel transistor has a first threshold voltage; and wherein the select transistor of each of the integer number N of data select paths is a p-channel transistor having a second threshold voltage lower than the first threshold voltage.

Claim 11

The dynamic multiplexer circuit of claim 8: wherein the first n-channel transistor has a first threshold voltage; and wherein the select transistor of each of the integer number N of data select paths is an n-channel transistor having a second threshold voltage lower than the first threshold voltage.

Claim 12

The dynamic multiplexer circuit of claim 1 wherein the precharge voltage comprises a first precharge voltage, and further comprising a precharge transistor connected to the output precharge node for precharging the output precharge node to a second precharge voltage during the precharge phase, wherein the second precharge voltage is unequal to the first precharge voltage.

Claim 13

The dynamic multiplexer circuit of claim 1, wherein the conditional series discharge path of each of the integer number N of data providing circuits comprises: a discharge transistor having its gate connected to receive a non-enabling signal during the precharge phase and an enabling signal during the evaluate phase; and at least one transistor having its source/drain connected in series with a source/drain of the discharge transistor.

Claim 14

The dynamic multiplexer circuit of claim 12: wherein the discharge transistor has a first threshold voltage; wherein the at least one transistor has a second threshold voltage; and wherein the second threshold voltage is lower than the first threshold voltage.

Claim 15

The dynamic multiplexer circuit of claim 12: wherein the discharge transistor has a first threshold voltage; wherein the at least one transistor has the first threshold voltage; and wherein the at least one transistor has its gate coupled to receive a non-enabling signal during the precharge phase.

Claim 16

A dynamic multiplexer circuit, comprising: an integer number N of data providing circuits, wherein the integer number N is greater than one and wherein each of the plurality of data providing circuits comprises: a precharge node to be precharged to a first precharge voltage during a precharge phase; a conditional series discharge path connected to the precharge node and operable in response to at least one enabling input signal to discharge the first precharge voltage at the precharge node during an evaluate phase thereby providing a first monotonic transitioning data signal at the precharge node; an inverter coupled to the precharge node and having an output for providing a second monotonic transitioning data signal, wherein the second monotonic transitioning data signal is complementary of the first monotonic transitioning data signal, wherein the inverter has an input and an output, and comprises: a first p-channel transistor having a source connected to a first voltage potential, a gate connected to the input of the inverter, and a drain connected to the output of the inverter; and a first n-channel transistor having a source connected to a second voltage potential lower than the first voltage potential, a gate connected to the input of the inverter, and a drain connected to the output of the inverter; the integer number N of data select paths, wherein each of the data select paths comprises a select transistor, the select transistor having a source coupled to receive the second monotonic transitioning data signal and a gate connected to receive a select signal; an output precharge node, wherein a drain of the select transistor in each of the data select paths is coupled to conditionally discharge the output precharge node; an output inverter having an input connected to the output precharge node; a precharge transistor connected to the output precharge node for precharging the output precharge node to a second precharge voltage during the precharge phase, wherein the second precharge voltage is unequal to the first precharge voltage; and wherein in a given evaluate phase of operation, in response to assertion of a select signal corresponding to one of the data select paths, the select transistor receiving the asserted select signal at its gate and the second monotonic transitioning data signal at its source conducts for providing an output data signal at an output of the output inverter, wherein the output data signal represents three signal inversions of the at least one enabling input signal.

Claim 17

A dynamic multiplexer circuit, comprising: an integer number N of data providing circuits, wherein the integer number N is greater than one and wherein each of the plurality of data providing circuits comprises: a precharge node to be precharged to a first precharge voltage during a precharge phase; a conditional series discharge path connected to the precharge node and operable in response to at least one enabling input signal to discharge the first precharge voltage at the precharge node during an evaluate phase thereby providing a first monotonic transitioning data signal at the precharge node; an inverter coupled to the precharge node and having an output for providing a second monotonic transitioning data signal, wherein the second monotonic transitioning data signal is complementary of the first monotonic transitioning data signal, wherein the inverter has an input and an output, and comprises: a first p-channel transistor having a source connected to a first voltage potential, a gate connected to the input of the inverter, and a drain connected to the output of the inverter; and a first n-channel transistor having a source connected to a second voltage potential lower than the first voltage potential, a gate connected to the input of the inverter, and a drain connected to the output of the inverter; the integer number N of data select paths, wherein each of the data select paths comprises a select transistor, the select transistor having a source coupled to receive the second monotonic transitioning data signal and a gate connected to receive a select signal; an output precharge node, wherein a drain of the select transistor in each of the data select paths is coupled to conditionally discharge the output precharge node; an output inverter having an input connected to the output precharge node; a precharge transistor connected to the output precharge node for precharging the output precharge node to a second precharge voltage during the precharge phase, wherein the second precharge voltage is unequal to the first precharge voltage; and wherein in a given evaluate phase of operation, in response to assertion of a select signal corresponding to one of the data select paths, the select transistor receiving the asserted select signal at its gate and the second monotonic transitioning data signal at its source conducts for providing an output data signal at an output of the output inverter, wherein the output data signal represents three signal inversions of the at least one enabling input signal.

Claim 18

The dynamic multiplexer circuit of claim 15: wherein the first p-channel transistor has a first threshold voltage; and wherein the select transistor of each of the integer number N of data select paths is a p-channel transistor having a second threshold voltage lower than the first threshold voltage.

Claim 19

The dynamic multiplexer circuit of claim 15: wherein the first n-channel transistor has a first threshold voltage; and wherein the select transistor of each of the integer number N of data select paths is an n-channel transistor having a second threshold voltage lower than the first threshold voltage.

Claim 20

The dynamic multiplexer circuit of claim 15, wherein the conditional series discharge path of each of the integer number N of data providing circuits comprises: a discharge transistor having its gate connected to receive a non-enabling signal during the precharge phase and an enabling signal during the evaluate phase; and at least one transistor having its source/drain connected in series with a source/drain of the discharge transistor.

Claim 21

The dynamic multiplexer circuit of claim 18: wherein the discharge transistor has a first threshold voltage; wherein the at least one transistor has a second threshold voltage; and wherein the second threshold voltage is lower than the first threshold voltage.

Claim 22

The dynamic multiplexer circuit of claim 18: wherein the discharge transistor has a first threshold voltage; wherein the at least one transistor has the first threshold voltage; and wherein the at least one transistor has its gate coupled to receive a non-enabling signal during the precharge phase.

Claim 23

The dynamic multiplexer circuit of claim 15: wherein the first p-channel transistor has a first threshold voltage; wherein the select transistor of each of the integer number N of data select paths is a p-channel transistor having a second threshold voltage lower than the first threshold voltage; wherein the conditional series discharge path of each of the integer number N of data providing circuits comprises: a discharge transistor having its gate connected to receive a non-enabling signal during the precharge phase and an enabling signal during the evaluate phase; and at least one transistor having its source/drain connected in series with a source/drain of the discharge transistor.

Claim 24

The dynamic multiplexer circuit of claim 21: wherein the discharge transistor has a third threshold voltage; wherein the at least one transistor has a fourth threshold voltage; and wherein the fourth threshold voltage is lower than the third threshold voltage.

Claim 25

The dynamic multiplexer circuit of claim 15: wherein the first n-channel transistor has a first threshold voltage; wherein the select transistor of each of the integer number N of data select paths is an n-channel transistor having a second threshold voltage lower than the first threshold voltage; wherein the conditional series discharge path of each of the integer number N of data providing circuits comprises: a discharge transistor having its gate connected to receive a non-enabling signal during the precharge phase and an enabling signal during the evaluate phase; and at least one transistor having its source/drain connected in series with a source/drain of the discharge transistor.

Claim 26

The dynamic multiplexer circuit of claim 23: wherein the discharge transistor has a third threshold voltage; wherein the at least one transistor has a fourth threshold voltage; and wherein the fourth threshold voltage is lower than the third threshold voltage.