Apparatus and method for allowing a dynamic logic gate to operation statically using subthreshold conduction precharging

Claim 2

The combination of a clock driver circuit and a dynamic logic circuit having an output, wherein (A) the logic circuit includes a precharge transistor that charges the output of the logic circuit to a first voltage level; and (B) the clock driver circuit provides a clock signal that provides a second voltage level and a third voltage level; wherein (i) the second voltage level turns on the precharge transistor, and (ii) the third voltage level is less than one threshold different from the first voltage level and causes the precharge transistor to operate in the subthreshold conduction region.

Claim 3

The dynamic logic circuit of claim 1, wherein the clock driver circuit comprises: (i) current source means for providing a reference current; (ii) transistor means for generating the third voltage level; and (iii) current control means coupled to the current source means and the transistor means for causing a constant bias current relative to the reference current to flow through the transistor means, wherein the third voltage level is dependent on the constant bias current.

Claim 4

The dynamic logic circuit of claim 2, wherein the transistor means comprises a pseudo-diode connected transistor.

Claim 5

The dynamic logic circuit of claim 2, wherein the transistor means comprises a diode connected transistor.

Claim 6

The dynamic logic circuit of claim 2, wherein the clock driver circuit further comprises delay means coupled to a control terminal of the transistor means for causing the transistor means to delay generating the third voltage level for a predetermined time interval, wherein during the predetermined time interval the transistor means generates a fourth voltage level that turns off the precharge transistor.

Claim 7

The dynamic logic circuit of claim 5, wherein the fourth voltage level is substantially equal to said first voltage level, wherein the delay means comprises a capacitance means and a resistance means, and wherein the predetermined time interval is derived from the resistance of the resistance means and the capacitance of the capacitance means.

Claim 8

The dynamic logic circuit of claim 6, wherein the resistance means includes a PFET and an NFET.

Claim 9

A dynamic logic circuit, coupled to a clock driver circuit providing a clock signal that has a precharge phase and an evaluate phase, comprising: (A) a logic network having a first end coupled to an output node wherein the logic network performs a predefined logic function; (B) at least one precharge transistor having a first terminal coupled to a first supply voltage, a second terminal coupled to the output node, and a control terminal coupled to receive the clock signal, wherein (i) during the precharge phase, the clock signal is at a first clock voltage level that turns on the precharge transistor and causes the turned on precharge transistor to charge the output node to a first output voltage level, and (ii) during the evaluate phase, the clock signal is at a second clock voltage level that is less than one threshold different from the first output voltage level and causes the precharge transistor to operate in the subthreshold conduction region; and (C) at least one evaluate transistor coupled to said logic network and having a control terminal coupled to receive the clock signal, wherein (i) during the precharge phase, the first clock voltage level turns off the evaluate transistor, and (ii) during the evaluate phase, the second clock voltage level turns on the evaluate transistor and the logic network selectively charges the output node to a second output voltage level in accordance with the predefined logic function.

Claim 10

A dynamic logic circuit, coupled to a clock driver circuit providing a clock signal that has a precharge phase and an evaluate phase, comprising: (A) a logic network having a first end coupled to an output node wherein the logic network performs a predefined logic function; (B) at least one precharge transistor having a first terminal coupled to a first supply voltage, a second terminal coupled to the output node, and a control terminal coupled to receive the clock signal, wherein (i) during the precharge phase, the clock signal is at a first clock voltage level that turns on the precharge transistor and causes the turned on precharge transistor to charge the output node to a first output voltage level, and (ii) during the evaluate phase, the clock signal is at a second clock voltage level that is less than one threshold different from the first output voltage level and causes the precharge transistor to operate in the subthreshold conduction region; and (C) at least one evaluate transistor coupled to said logic network and having a control terminal coupled to receive the clock signal, wherein (i) during the precharge phase, the first clock voltage level turns off the evaluate transistor, and (ii) during the evaluate phase, the second clock voltage level turns on the evaluate transistor and the logic network selectively charges the output node to a second output voltage level in accordance with the predefined logic function.

Claim 11

The dynamic logic circuit of claim 8, wherein the precharge transistor's subthreshold operation during the evaluate phase maintains the output node at the first output voltage level when the logic network does not charge the output node to the second output voltage level and wherein said logic network is a portion of a memory cell in a memory array or a programmed logic array.

Claim 12

The dynamic logic circuit of claim 8, wherein the clock driver circuit comprises: (i) current source means for providing a reference current; (ii) transistor means for generating the second clock voltage level; and (iii) current control means coupled to the current source means and the transistor means for causing a constant bias current relative to the reference current to flow through the transistor means wherein the second clock voltage level is dependent on the constant bias current.

Claim 13

The dynamic logic circuit of claim 10, wherein the transistor means comprises a pseudo-diode connected transistor.

Claim 14

The dynamic logic circuit of claim 10, wherein the transistor means comprises a diode connected transistor.

Claim 15

The dynamic logic circuit of claim 10, wherein the clock driver circuit further comprises delay means coupled to a control terminal of the transistor means for causing the transistor means to delay generating the second clock voltage level for an initial period of the evaluate phase, wherein during the initial period of the evaluate phase the clock signal completely turns off the precharge transistor.

Claim 16

The dynamic logic circuit of claim 13, wherein the delay means comprises a resistance means and capacitance means.

Claim 17

The dynamic logic circuit of claim 10, wherein the precharge transistor is a P-channel transistor, the evaluate transistor is a N-channel transistor, and the logic network is an NFET logic network.

Claim 18

The dynamic logic circuit of claim 10, wherein the precharge transistor is a N-channel transistor, the evaluate transistor is a P-channel transistor, and the logic network is a PFET logic network.

Claim 19

A dynamic logic circuit, comprising: (A) a logic network circuit having a first end coupled to an output node and a second end, wherein the logic network circuit is coupled to receive at least one logic input for performing a predefined logic function with respect to the logic input; (B) precharging transistor for precharging the output node to a first voltage state, wherein the precharging transistor means includes a first terminal coupled to a first supply voltage, a second main terminal coupled to the output node, and a control terminal; (C) evaluation transistor for allowing the logic network circuit to selectively charge the output node to a second voltage state in accordance with the predefined logic function with respect to the logic input, wherein the evaluation means includes a first terminal coupled to the second end of the logic network circuit, a second terminal coupled to a second supply voltage, and a control terminal; (D) circuitry coupled to the control terminal of the precharging transistor and evaluation transistor, wherein the circuitry further comprises (i) a current source for providing a reference current; (ii) a first transistor for generating a bias voltage, wherein the bias voltage has a voltage level that is less than one threshold voltage different from the first voltage state and causes the precharging transistor to operate in the subthreshold conduction region; (iii) current control means coupled to the current source and the first transistor for causing a constant current relative to the reference current to flow through the first transistor such that the first transistor generates the bias voltage; (iv) switching means coupled to the first transistor and being responsive to a control signal for selectively coupling the control terminal of the precharging transistor and evaluation transistor to one of (1) the control signal and (2) the bias voltage, wherein when the switching means couples the control terminal of the precharging transistor and the evaluation transistor to the control signal under the control of the control signal, the precharging transistor is turned on and the evaluation transistor is turned off such that the output node is charged to the first voltage state, wherein when the switching causes the control terminal of the precharging transistor and evaluation transistor to receive the bias voltage under the control of the control signal, (1) the evaluation transistor is turned on to allow the logic network circuit to selectively charge the output node to the second voltage state according to the predefined logic function of the logic input and (2) the precharging transistor is turned to operate in a subthreshold conduction region so as to allow a substantially reduced current to flow through to maintain the output node at the first voltage state when the logic network circuit does not charge the output node to the second voltage state such that the dynamic logic gate circuit can operate statically.

Claim 20

A dynamic logic circuit, comprising: (A) a logic network circuit having a first end coupled to an output node and a second end, wherein the logic network circuit is coupled to receive at least one logic input for performing a predefined logic function with respect to the logic input; (B) precharging transistor for precharging the output node to a first voltage state, wherein the precharging transistor means includes a first terminal coupled to a first supply voltage, a second main terminal coupled to the output node, and a control terminal; (C) evaluation transistor for allowing the logic network circuit to selectively charge the output node to a second voltage state in accordance with the predefined logic function with respect to the logic input, wherein the evaluation means includes a first terminal coupled to the second end of the logic network circuit, a second terminal coupled to a second supply voltage, and a control terminal; (D) circuitry coupled to the control terminal of the precharging transistor and evaluation transistor, wherein the circuitry further comprises (i) a current source for providing a reference current; (ii) a first transistor for generating a bias voltage, wherein the bias voltage has a voltage level that is less than one threshold voltage different from the first voltage state and causes the precharging transistor to operate in the subthreshold conduction region; (iii) current control means coupled to the current source and the first transistor for causing a constant current relative to the reference current to flow through the first transistor such that the first transistor generates the bias voltage; (iv) switching means coupled to the first transistor and being responsive to a control signal for selectively coupling the control terminal of the precharging transistor and evaluation transistor to one of (1) the control signal and (2) the bias voltage, wherein when the switching means couples the control terminal of the precharging transistor and the evaluation transistor to the control signal under the control of the control signal, the precharging transistor is turned on and the evaluation transistor is turned off such that the output node is charged to the first voltage state, wherein when the switching causes the control terminal of the precharging transistor and evaluation transistor to receive the bias voltage under the control of the control signal, (1) the evaluation transistor is turned on to allow the logic network circuit to selectively charge the output node to the second voltage state according to the predefined logic function of the logic input and (2) the precharging transistor is turned to operate in a subthreshold conduction region so as to allow a substantially reduced current to flow through to maintain the output node at the first voltage state when the logic network circuit does not charge the output node to the second voltage state such that the dynamic logic gate circuit can operate statically.

Claim 21

The dynamic logic circuit of claim 17, wherein the circuitry further comprises delay means coupled to a control terminal of the first transistor for causing the first transistor to delay generating the bias voltage for a predetermined time interval after the precharging transistor is completely turned off by the control signal.

Claim 22

The dynamic logic circuit of claim 18, wherein the precharging transistor comprises an NFET and the evaluation transistor comprises a PFET, and wherein the logic network circuit comprises a PFET logic network circuit.

Claim 23

The dynamic logic circuit of claim 17, wherein the precharging transistor comprises a PFET and the evaluation transistor comprises an NFET, wherein the logic network circuit is an NFET logic network circuit.

Claim 24

A clock driver circuit providing a clock signal (A) wherein the clock signal comprises: (i) a first voltage level that causes a transistor of a first conductivity type to operate in the subthreshold conduction region, and (ii) a second voltage level that causes a transistor of a conductivity type complementary to the first conductivity type to operate in the subthreshold conduction region; and (B) wherein the clock driver circuit comprises: (i) a first current source means for providing a first reference current, (ii) a first transistor means for generating the first voltage level, (iii) a first current control means coupled to the first current source means and to the first transistor means for causing a first constant current relative to the reference current to flow through the first transistor means, wherein the first voltage level is dependent on the first constant current, (iv) a second current source means for providing a second reference current, (v) a second transistor means for generating the second voltage level, and (vi) a second current control means coupled to the second current source means and to the second transistor means for causing a second constant current relative to the second reference current to flow through the second transistor means, wherein the second voltage level is dependent on the second constant current.

Claim 25

A clock driver circuit providing a clock signal (A) wherein the clock signal comprises: (i) a first voltage level that causes a transistor of a first conductivity type to operate in the subthreshold conduction region, and (ii) a second voltage level that causes a transistor of a conductivity type complementary to the first conductivity type to operate in the subthreshold conduction region; and (B) wherein the clock driver circuit comprises: (i) a first current source means for providing a first reference current, (ii) a first transistor means for generating the first voltage level, (iii) a first current control means coupled to the first current source means and to the first transistor means for causing a first constant current relative to the reference current to flow through the first transistor means, wherein the first voltage level is dependent on the first constant current, (iv) a second current source means for providing a second reference current, (v) a second transistor means for generating the second voltage level, and (vi) a second current control means coupled to the second current source means and to the second transistor means for causing a second constant current relative to the second reference current to flow through the second transistor means, wherein the second voltage level is dependent on the second constant current.

Claim 28

The method of claim 22, further comprising the step of delaying applying the bias voltage to the precharge transistor for a predetermined time interval after the precharge transistor is turned off by the control signal.

Claim 29

The method of claim 23, wherein the step (B) further comprises a step of turning on an evaluate transistor coupled to the logic network circuit by the control signal to allow the logic network circuit to selectively charge the output node to the second voltage state.

Claim 30

A logic circuit comprising: a latch/logic circuit having an internal logic state storage node; a feedback enabling transistor coupled to said latch/logic circuit, said feedback enabling transistor enabling feedback to maintain a latched data state of said internal logic state storage node: a clock driver circuit coupled to said feedback enabling transistor, said clock driver circuit providing a clock signal having a first voltage level and a second voltage level, wherein said first voltage level turns on said feedback enabling transistor and said second voltage level causes the feedback enabling transistor to operate in a subthreshold conduction region to maintain said latched data state of said internal logic state storage node.

Claim 31

A logic circuit comprising: a latch/logic circuit having an internal logic state storage node; a feedback enabling transistor coupled to said latch/logic circuit, said feedback enabling transistor enabling feedback to maintain a latched data state of said internal logic state storage node: a clock driver circuit coupled to said feedback enabling transistor, said clock driver circuit providing a clock signal having a first voltage level and a second voltage level, wherein said first voltage level turns on said feedback enabling transistor and said second voltage level causes the feedback enabling transistor to operate in a subthreshold conduction region to maintain said latched data state of said internal logic state storage node.

Claim 32

A logic circuit as in claim 25 further comprising a further feedback enabling transistor, said further feedback enabling transistor being coupled to said latch/logic circuit and a further clock driver circuit coupled to said further feedback enabling transistor, said further clock driver circuit providing a clock signal having a third voltage level and a fourth voltage level, wherein said third voltage level turns on said further feedback enabling transistor and said fourth voltage level causes the further feedback enabling transistor to operate in another subthreshold conduction region.

Claim 33

A logic circuit as in claim 25 wherein the clock driver circuit comprises: (i) current source means for providing a reference current; (ii) first transistor means for generating the second voltage level; and (iii) current control means coupled to the current source means and the first transistor means for causing a constant bias current relative to the reference current to flow through the first transistor means, wherein the second voltage level is dependent on the constant bias current.

Claim 34

The logic circuit of claim 27, wherein the first transistor means comprises a pseudo-diode connected transistor.

Claim 35

The logic circuit of claim 27, wherein the first transistor means comprises a diode connected transistor.

Claim 36

The logic circuit of claim 27, wherein the clock driver circuit further comprises delay means coupled to a control terminal of the first transistor means for causing the transistor means to delay generating the second voltage level for a predetermined time interval, wherein during the predetermined time interval the transistor means generates a third voltage level that turns off the feedback enabling transistor.

Claim 37

The logic circuit of claim 30, wherein the delay means comprises a capacitance means and a resistance means, and wherein the predetermined time interval is derived from the resistance of the resistance means and the capacitance of the capacitance means.