Mitigating the adverse effects of charge sharing in dynamic logic circuits

Claim 3

The system of claim 1, wherein three transistors converge at said node, said three transistors configured on said substrate so that said common interstitial space exhibits a T-like configuration.

Claim 4

The system of claim 1, wherein four transistors converge at said node, said four transistors configured on said substrate so that said common interstitial space exhibits a cross-like configuration.

Claim 5

A mousetrap logic gate comprising the system of claim 3.

Claim 10

The method of claim 6, further comprising the step of situating in close proximity transistor gates so that parasitic capacitance is minimized.

Claim 13

The system of claim 8, wherein said precharging means comprises a PMOSFET switched concurrently with said arming means.

Claim 14

The system of claim 8, wherein said precharging means comprises an NMOSFET switched concurrently with said arming means.

Claim 15

The system of claim 8, wherein said precharging means is connected to a common substrate shared by at least three converging transistors which converge at said node so that a region of each transistor gate is adjacent a region of each of the other remaining transistor gates.

Claim 16

A mousetrap logic gate comprising the system of claim 8.

Claim 19

The system of claim 13, wherein transistor gates of said plurality of said transistors are situated in close proximity so that parasitic capacitance is minimized.

Claim 20

A mousetrap logic gate comprising the system of claim 13.

Claim 23

The method of claim 16, further comprising the step of forming a T-like configuration with said common interstitial space.

Claim 24

The method of claim 16, further comprising the step of forming a cross-like configuration with said common interstitial space.

Claim 25

The method of claim 16, further comprising the step of forming said common interstitial space in a mousetrap logic gate.

Claim 28

The system of claim 20, wherein said common substrate exhibits a T-like configuration.

Claim 29

The system of claim 20, wherein said common substrate exhibits a cross-like configuration.

Claim 30

A logic gate for a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit a logic low, each of said valid states exhibited when a subset of said logic paths exhibit a logic high, the logic gate for deriving an output vector from input vectors, the logic gate for mitigating the adverse effects of charge sharing by manipulating the physical layout of transistors, comprising: logic means comprising a plurality of ladder logic mechanisms, said logic mechanisms for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logic mechanisms, said inverting buffer mechanisms configured to output corresponding vector components defining said output vector, said inverting buffer means for maintaining said vector components at a logic low before receiving said ladder logic outputs so that said output vector exhibits said invalid state, one of said inverting buffer mechanisms configured to receive said vector logic output and invert said ladder logic output to thereby derive said output vector in said valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at said logic low; and said logic means having at least three transistors situated on a substrate with a common interstitial space separating their gates so that each gate is adjacent to two other gates of the remaining transistors.

Claim 31

A logic gate for a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit a logic low, each of said valid states exhibited when a subset of said logic paths exhibit a logic high, the logic gate for deriving an output vector from input vectors, the logic gate for mitigating the adverse effects of charge sharing by manipulating the physical layout of transistors, comprising: logic means comprising a plurality of ladder logic mechanisms, said logic mechanisms for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logic mechanisms, said inverting buffer mechanisms configured to output corresponding vector components defining said output vector, said inverting buffer means for maintaining said vector components at a logic low before receiving said ladder logic outputs so that said output vector exhibits said invalid state, one of said inverting buffer mechanisms configured to receive said vector logic output and invert said ladder logic output to thereby derive said output vector in said valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at said logic low; and said logic means having at least three transistors situated on a substrate with a common interstitial space separating their gates so that each gate is adjacent to two other gates of the remaining transistors.

Claim 32

The system of claim 23, wherein three transistors converge at said node, said three transistors configured on said substrate so that said common interstitial space exhibits a T-like configuration.

Claim 33

The system of claim 23, wherein four transistors converge at said node, said four transistors configured on said substrate so that said common interstitial space exhibits a cross-like configuration.

Claim 34

The system of claim 23, wherein said inverting buffer mechanisms each comprise a CMOSFET inverter having a CMOSFET output which switches faster from a logic low to a logic high than from a logic high to a logic low.

Claim 35

The system of claim 23, wherein said logic means further comprises another node where a plurality of transistors connected in a ladder-like manner converge, and further comprising a precharging means for precharging said another node when said inverting buffer mechanisms are precharged by said arming mechanisms.

Claim 36

The system of claim 27, wherein said precharging means comprises a PMOSFET which is switched when said arming mechanisms precharge said inverting buffer mechanisms.

Claim 37

The system of claim 27, wherein said precharging means comprises a NMOSFET which is switched when said arming mechanisms precharge said inverting buffer mechanisms.

Claim 40

The method of claim 30, further comprising the step of forming a T-like configuration with said common interstitial space.

Claim 41

The method of claim 30, further comprising the step of forming a cross-like configuration with said common interstitial space.

Claim 42

The method of claim 30, further comprising the step of disposing a precharging means at another node in said logic means where transistors converge, said precharging means for precharging said another node when said inverting buffer input is precharged by said arming means.

Claim 43

The method of claim 30, further comprising the step of implementing said inverting buffer means with a CMOSFET inverter having a PMOSFET width which is greater than an NMOSFET width so that said CMOSFET inverter switches quicker from a first logic state to a second logic state than from said second logic state to said first logic state.