Vector logic method and dynamic mousetrap logic gate for a self-timed monotonic logic progression

Claim 3

The method of claim 1, further comprising the step of defining a further subset of said subset as an invalid vector logic state.

Claim 4

The method of claim 1, further comprising the step of performing an inclusive OR logic function on vector logic variables at said gate inputs.

Claim 5

The method of claim 1, further comprising the step of performing an add predecoder logic function on vector logic variables at said gate inputs.

Claim 6

The method of claim 1, further comprising the step of performing a carry propagate logic function on vector logic variables at said gate inputs.

Claim 7

The method of claim 1, further comprising the step of performing an exclusive OR logic function on vector logic variables at said gate inputs.

Claim 8

The method of claim 1, further comprising the step of performing a Y encoder logic function on vector logic variables at said gate inputs.

Claim 9

The method of claim 1, further comprising the step of generating partial products from vector logic variables at said gate inputs.

Claim 10

The method of claim 1, further comprising the step of performing ternary ripple carry addition on vector logic variables at said gate inputs.

Claim 11

The method of claim 1, wherein said subset is two in number.

Claim 12

The method of claim 1, wherein said gate inputs number at least three.

Claim 13

The method of claim 1, further comprising the step of encoding more than one invalid logic state with said vector logic variable.

Claim 14

The method of claim 1, further comprising the step of encoding a non-Boolean variable with said vector logic variable.

Claim 15

The method of claim 1, further comprising the step of employing said logic gate in an adder logic circuit.

Claim 16

The method of claim 1, further comprising the step of employing said logic gate within a multiplier logic circuit.

Claim 17

A logic gate for a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said subset is greater than one.

Claim 18

A logic gate for a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said subset is greater than one.

Claim 19

The logic gate of claim 16, wherein either an input vector or said output vector, or both, comprises a vector logic variable defined by at least three of said vector components.

Claim 20

The logic gate of claim 16, wherein said logic means is configured so that an inclusive OR logic operation is performed on said input vectors to derive said output vector.

Claim 21

The logic gate of claim 16, wherein said logic means is configured so that an add predecoder logic operation is performed on said input vectors to derive said output vector.

Claim 22

The logic gate of claim 16, wherein said logic means is configured to perform a carry propagate logic operation on said input vectors to derive said output vector.

Claim 23

The logic gate of claim 16, wherein said logic means is configured so that an exclusive OR logic operation is performed on said input vectors to derive said output vector.

Claim 24

The logic gate of claim 16, wherein said logic means is configured so that a Y encoder logic operation for Booth's algorithm is performed on said input vectors to derive said output vector.

Claim 25

The logic gate of claim 16, wherein said logic means is configured so that a partial product generation operation is performed on said input vectors to derive said output vector.

Claim 26

The logic gate of claim 16, wherein said logic means is configured so that a ternary ripple carry addition operation is performed on said input vectors to derive said output vector.

Claim 27

The logic gate of claim 16, wherein said subset is two in number.

Claim 28

The logic gate of claim 16, wherein each of said ladder logics comprises an n-channel metal oxide semiconductor field effect transistor (MOSFET).

Claim 29

The logic gate of claim 16, wherein each of said inverting buffer mechanisms comprises a complementary metal oxide semiconductor field effect transistor (CMOSFET).

Claim 30

The logic gate of claim 16, wherein each of said arming mechanisms comprises a p-channel metal oxide semiconductor field effect transistor (MOSFET).

Claim 31

The logic gate of claim 16, wherein one of said input vectors defines a non-Boolean logic variable.

Claim 32

The logic gate of claim 16, wherein said output vector defines a non-Boolean logic variable.

Claim 33

The logic gate of claim 16, wherein said logic gate is cascaded with at least two other cascaded logic gates.

Claim 34

The logic gate of claim 16, wherein said logic gate is employed within an adder logic circuit.

Claim 35

The logic gate of claim 16, wherein said logic gate is employed within a multiplier logic circuit.

Claim 36

The logic gate of claim 16, wherein said logic gate is employed within a means for providing floating point operations.

Claim 37

A vector logic gate for performing a monotonic logic progression, the vector logic gate comprising: n logic paths; a vector logic variable encoded on said n logic paths and having k valid vector logic states; m of said n logic paths defining each of said k vector logic states; wherein k≦i and i=(n!)/(m! (n-m)!); and wherein m>2.

Claim 38

A vector logic gate for performing a monotonic logic progression, the vector logic gate comprising: n logic paths; a vector logic variable encoded on said n logic paths and having k valid vector logic states; m of said n logic paths defining each of said k vector logic states; wherein k≦i and i=(n!)/(m! (n-m)!); and wherein m>2.

Claim 39

The logic gate of claim 35, wherein said vector logic variable exhibits either an invalid state or a valid state at an instant in time, said invalid state exhibited when all of said n logic paths exhibit a logic low, said valid state exhibited when said subset m of said n logic paths exhibit a logic high.

Claim 40

The logic gate of claim 35, wherein m≦(1/2)(n).

Claim 41

The logic gate of claim 35, further comprising: logic means comprising a plurality of ladder logics, said logic means for receiving inputs, for performing logic functions upon said inputs, and for providing ladder logic outputs from said ladder logics; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output signals on said n logic paths to define each of said k vector logic states, said inverting buffer mechanisms configured to maintain said n logic paths at logic low before receiving m ladder logic signals on said ladder logic outputs, m of said inverting buffer mechanisms configured to receive and invert said m ladder logic signals to derive one of said k vector logic states; and arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said n logic paths at logic low.

Claim 42

The logic gate of claim 35, further comprising: logic means comprising a plurality of ladder logics, said logic means for receiving inputs on said n logic paths, for performing logic functions upon said inputs and for providing ladder logic outputs from said ladder logics; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to receive ladder logic signals on said ladder logic outputs and invert said signals to derive a vector logic variable output; and arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain logic paths defining said output vector at logic low.

Claim 43

The logic gate of claim 35, wherein said vector logic variable has an invalid vector logic state for permitting self-timing.

Claim 44

A methods for performing a self-timed monotonic logic progression in a logic gate comprising gate components configured in parallel, each of said gate components comprising a ladder logic connected to a plurality of gate inputs and to an inverting buffer mechanism, the inverting buffer mechanism for providing a gate output after receipt of a ladder logic output, and an arming mechanism for periodically precharging the inverting buffer mechanism to drive said gate output to logic low until said inverting buffer mechanism is triggered by said ladder logic output, the method comprising the steps of: encoding a vector logic variable by a set of vector components of said gate inputs; and encoding timing information in said vector logic variable by defining an invalid vector logic state when all said vector components concurrently exhibit logic low and by defining a unique one of a plurality of valid vector logic states when a subset of said set of vector components exhibits logic high, wherein said subset is nonoverlapping relative to other subsets corresponding with other valid vector logic states, and wherein said subset is greater than one in number.

Claim 45

A methods for performing a self-timed monotonic logic progression in a logic gate comprising gate components configured in parallel, each of said gate components comprising a ladder logic connected to a plurality of gate inputs and to an inverting buffer mechanism, the inverting buffer mechanism for providing a gate output after receipt of a ladder logic output, and an arming mechanism for periodically precharging the inverting buffer mechanism to drive said gate output to logic low until said inverting buffer mechanism is triggered by said ladder logic output, the method comprising the steps of: encoding a vector logic variable by a set of vector components of said gate inputs; and encoding timing information in said vector logic variable by defining an invalid vector logic state when all said vector components concurrently exhibit logic low and by defining a unique one of a plurality of valid vector logic states when a subset of said set of vector components exhibits logic high, wherein said subset is nonoverlapping relative to other subsets corresponding with other valid vector logic states, and wherein said subset is greater than one in number.

Claim 48

A mousetrap logic gate for performing an add predecoder logic function on vector logic variables and for performing a self-timed monotonic logic progression, each of the vector logic variables defined by vector components on respective logic paths, each vector logic variable exhibiting an invalid state when all of said logic paths exhibit logic low, each vector logic variable exhibiting a unique one of a plurality of possible valid states when a subset of said logic paths exhibits logic high, the gate for deriving an output vector generated from an add predecoder logic operation on input vectors, comprising: logic means comprising three ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic outputs from said ladder logics; buffer means comprising three inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output vector components defining said output vector, said output vector having three valid states, said three valid states including a carry propagate state, a carry kill state, and a carry generate state, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving a ladder logic signal from said ladder logic outputs so that said output vector exhibits said invalid state, one of said inverting buffer mechanisms configured to receive and invert said ladder logic signal to thereby derive said output vector in one of said three valid states; and arming means comprising three arming mechanisms associated respectively with said inverted buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components of said output vector at logic low.

Claim 49

A mousetrap logic gate for performing an add predecoder logic function on vector logic variables and for performing a self-timed monotonic logic progression, each of the vector logic variables defined by vector components on respective logic paths, each vector logic variable exhibiting an invalid state when all of said logic paths exhibit logic low, each vector logic variable exhibiting a unique one of a plurality of possible valid states when a subset of said logic paths exhibits logic high, the gate for deriving an output vector generated from an add predecoder logic operation on input vectors, comprising: logic means comprising three ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic outputs from said ladder logics; buffer means comprising three inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output vector components defining said output vector, said output vector having three valid states, said three valid states including a carry propagate state, a carry kill state, and a carry generate state, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving a ladder logic signal from said ladder logic outputs so that said output vector exhibits said invalid state, one of said inverting buffer mechanisms configured to receive and invert said ladder logic signal to thereby derive said output vector in one of said three valid states; and arming means comprising three arming mechanisms associated respectively with said inverted buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components of said output vector at logic low.

Claim 50

A mousetrap logic gate for performing a carry propagate logic function on vector logic variables and for performing a self-timed monotonic logic progression, each of the vector logic variables defined by vector components on respective logic paths, each vector logic variable exhibiting an invalid state when all of said logic paths exhibit logic low, each of the vector logic variables exhibiting a unique one of a plurality of possible valid states when a subset of said logic paths exhibits logic high, the logic gate for deriving an output vector generated from a carry propagate logic operation on input vectors, comprising: logic means comprising two ladder logics, said logic means for receiving two input vectors, one input vector defining a carry logic state, another input vector defining carry kill, propagate, and generate states, said logic means for performing logic functions upon said input vectors, and for providing ladder logic outputs from said ladder logics; buffer means comprising two inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output two vector components defining a carryout output vector, said inverting buffer mechanisms configured to maintain said two vector components at logic low before receiving a ladder logic signal from said logic means so that said carryout output vector exhibits said invalid state, one of said inverting buffer mechanisms configured to receive and invert said ladder logic signal to thereby derive said carryout output vector in said valid state; and arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said two vector components of said output vector at logic low.

Claim 51

A mousetrap logic gate for performing a carry propagate logic function on vector logic variables and for performing a self-timed monotonic logic progression, each of the vector logic variables defined by vector components on respective logic paths, each vector logic variable exhibiting an invalid state when all of said logic paths exhibit logic low, each of the vector logic variables exhibiting a unique one of a plurality of possible valid states when a subset of said logic paths exhibits logic high, the logic gate for deriving an output vector generated from a carry propagate logic operation on input vectors, comprising: logic means comprising two ladder logics, said logic means for receiving two input vectors, one input vector defining a carry logic state, another input vector defining carry kill, propagate, and generate states, said logic means for performing logic functions upon said input vectors, and for providing ladder logic outputs from said ladder logics; buffer means comprising two inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output two vector components defining a carryout output vector, said inverting buffer mechanisms configured to maintain said two vector components at logic low before receiving a ladder logic signal from said logic means so that said carryout output vector exhibits said invalid state, one of said inverting buffer mechanisms configured to receive and invert said ladder logic signal to thereby derive said carryout output vector in said valid state; and arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said two vector components of said output vector at logic low.

Claim 52

A mousetrap logic gate for performing an exclusive OR logic function on vector logic variables and for performing a self-timed monotonic logic progression, each of the vector logic variables defined by vector components on respective logic paths, each vector logic variable exhibiting an invalid state when all of said logic paths exhibit logic low, each of the vector logic variables exhibiting a unique one of a plurality of possible valid states when a subset of said logic paths exhibits logic high the logic gate for deriving an output vector generated from an exclusive OR logic operation on input vectors, the logic gate comprising: logic means comprising a ladder logic, said logic means for receiving at least two input vectors, each of said input vectors comprising two input vector components, said logic means for performing logic functions upon said input vectors and for providing ladder logic outputs from said ladder logics; buffer means comprising two inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said output vector having two output vector components, said inverting buffer mechanisms configured to maintain said two output vector components of said output vector at logic low prior to receiving a ladder logic signal on said ladder logic outputs so that said output vector exhibits said invalid state, one of said inverting buffer mechanisms configured to receive and invert said ladder logic signal to thereby derive said output vector in said valid state; arming means comprising two arming mechanisms associated respectively with said inverting buffer mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said two output vector components of said output vector at logic low; and said logic means, said buffer means, and said arming means, in combination, adapted to perform sad exclusive OR logic operation on said input vectors to derive said output vector.

Claim 53

A mousetrap logic gate for performing an exclusive OR logic function on vector logic variables and for performing a self-timed monotonic logic progression, each of the vector logic variables defined by vector components on respective logic paths, each vector logic variable exhibiting an invalid state when all of said logic paths exhibit logic low, each of the vector logic variables exhibiting a unique one of a plurality of possible valid states when a subset of said logic paths exhibits logic high the logic gate for deriving an output vector generated from an exclusive OR logic operation on input vectors, the logic gate comprising: logic means comprising a ladder logic, said logic means for receiving at least two input vectors, each of said input vectors comprising two input vector components, said logic means for performing logic functions upon said input vectors and for providing ladder logic outputs from said ladder logics; buffer means comprising two inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said output vector having two output vector components, said inverting buffer mechanisms configured to maintain said two output vector components of said output vector at logic low prior to receiving a ladder logic signal on said ladder logic outputs so that said output vector exhibits said invalid state, one of said inverting buffer mechanisms configured to receive and invert said ladder logic signal to thereby derive said output vector in said valid state; arming means comprising two arming mechanisms associated respectively with said inverting buffer mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said two output vector components of said output vector at logic low; and said logic means, said buffer means, and said arming means, in combination, adapted to perform sad exclusive OR logic operation on said input vectors to derive said output vector.

Claim 54

A mousetrap logic gate for performing a Y encoder logic function for Booth's algorithm and for performing a self-timed monotonic logic progression utilizing vector logic variables, and for implementing a self-timed monotonic logic progression utilizing vector variables, each of the vector logic variables defined by vector components on respective logic paths, each of the vector logic variables exhibiting an invalid state when all of said logic paths exhibit logic low, each of the vector logic variables exhibiting a unique one of a plurality of possible valid states when a subset of said logic paths exhibits logic high, the logic gate for deriving an output vector with four output vector components encoding six operation codes from three input vectors, each of said three input vectors having two vector components, each said two input vector components defining a Y-operand, comprising: logic means comprising four ladder logics, said logic means for receiving said input vectors for performing logic functions upon said input vectors, and for providing ladder logic signals on ladder logic outputs; buffer means comprising four inverting buffer mechanisms associated respectively with said ladder logics and connected to said ladder logic outputs, said inverting buffer mechanisms configured to output said four output vector components of said output vector, said inverting buffer mechanisms configured to maintain said four output vector components at logic low before receiving a ladder logic signal from said ladder logic outputs so that said output vector exhibits said invalid state, two of said inverting buffer mechanisms configured to permit two of said four vector components to transcend from logic low to logic high after receiving said ladder logic signals on said ladder logic outputs to thereby derive said output vector in said valid state; and arming means comprising four arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said four output vector components at said logic low.

Claim 55

A mousetrap logic gate for performing a Y encoder logic function for Booth's algorithm and for performing a self-timed monotonic logic progression utilizing vector logic variables, and for implementing a self-timed monotonic logic progression utilizing vector variables, each of the vector logic variables defined by vector components on respective logic paths, each of the vector logic variables exhibiting an invalid state when all of said logic paths exhibit logic low, each of the vector logic variables exhibiting a unique one of a plurality of possible valid states when a subset of said logic paths exhibits logic high, the logic gate for deriving an output vector with four output vector components encoding six operation codes from three input vectors, each of said three input vectors having two vector components, each said two input vector components defining a Y-operand, comprising: logic means comprising four ladder logics, said logic means for receiving said input vectors for performing logic functions upon said input vectors, and for providing ladder logic signals on ladder logic outputs; buffer means comprising four inverting buffer mechanisms associated respectively with said ladder logics and connected to said ladder logic outputs, said inverting buffer mechanisms configured to output said four output vector components of said output vector, said inverting buffer mechanisms configured to maintain said four output vector components at logic low before receiving a ladder logic signal from said ladder logic outputs so that said output vector exhibits said invalid state, two of said inverting buffer mechanisms configured to permit two of said four vector components to transcend from logic low to logic high after receiving said ladder logic signals on said ladder logic outputs to thereby derive said output vector in said valid state; and arming means comprising four arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said four output vector components at said logic low.

Claim 56

A mousetrap logic gate for generating partial products for Booth's algorithm and for implementing a self-timed monotonic logic progression utilizing vector logic variables, each of the vector logic variables defined by vector components on respective logic paths, each of the vector logic variables exhibiting an invalid state when all of said logic paths exhibit logic low, each of the vector logic variable exhibiting a unique one of a plurality of possible valid state when a subset of said logic paths exhibits logic high, the logic gate for deriving an output vector with two output vector components defining a partial product from two input vectors, the two input vectors comprising an X operand vector with two vector components for defining an X operand and an operation code vector with four input vector components for defining six operation codes, comprising; logic means comprising two ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing ladder logic outputs from said ladder logics; buffer means comprising two inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said output vector, said inverting buffer mechanisms configured to maintain said two output vector components of said output vector at logic low before receiving a ladder logic signal on said ladder logic outputs so that said output vector exhibits said invalid state, one of said inverting buffer mechanisms configured to output logic high after receiving said ladder logic signals on said ladder logic outputs; arming means comprising two arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured-to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said two output vector components of said output vector at logic low; and said logic means, said buffer means, and said arming means, in combination, adapted to generate said output vector which defines said partial products for said Booth's algorithm from said input vectors.

Claim 57

A mousetrap logic gate for generating partial products for Booth's algorithm and for implementing a self-timed monotonic logic progression utilizing vector logic variables, each of the vector logic variables defined by vector components on respective logic paths, each of the vector logic variables exhibiting an invalid state when all of said logic paths exhibit logic low, each of the vector logic variable exhibiting a unique one of a plurality of possible valid state when a subset of said logic paths exhibits logic high, the logic gate for deriving an output vector with two output vector components defining a partial product from two input vectors, the two input vectors comprising an X operand vector with two vector components for defining an X operand and an operation code vector with four input vector components for defining six operation codes, comprising; logic means comprising two ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing ladder logic outputs from said ladder logics; buffer means comprising two inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said output vector, said inverting buffer mechanisms configured to maintain said two output vector components of said output vector at logic low before receiving a ladder logic signal on said ladder logic outputs so that said output vector exhibits said invalid state, one of said inverting buffer mechanisms configured to output logic high after receiving said ladder logic signals on said ladder logic outputs; arming means comprising two arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured-to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said two output vector components of said output vector at logic low; and said logic means, said buffer means, and said arming means, in combination, adapted to generate said output vector which defines said partial products for said Booth's algorithm from said input vectors.

Claim 58

A mousetrap logic gate for implementing a ternary addition operation and for implementing a self-timed monotonic logic progression utilizing vector logic variables, each of the vector logic variables defined by vector components on respective logic paths, each of the vector logic variables exhibiting an invalid state when all of said logic paths exhibit logic low, each of the vector logic variables exhibiting a unique one of a plurality of possible valid states when a subset of said logic paths exhibits logic high, the gate for deriving a sum output vector with three vector components and a carry output vector with two vector components from three input vectors including a first operand with three vector components, a second operand with three vector components, and a carry operand with two vector components, comprising: logic means comprising ten ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing ladder logic outputs; buffer means comprising ten inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said output vector, said inverting buffer mechanisms configured to maintain said vector components of said output vectors at logic low before receiving a ladder logic signal on said ladder logic outputs so that said output vectors exhibit said invalid state, sad inverting buffer mechanisms configured to receive said ladder logic signal on said ladder logic outputs and to invert said ladder logic signal to thereby derive said output vectors in said valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, sad arming mechanisms configured to precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components of said output vectors at logic low; and said logic means, said buffer means, and said arming means, in combination, adapted to perform said ternary addition operation on said input vectors to derive said output vectors.

Claim 59

A mousetrap logic gate for implementing a ternary addition operation and for implementing a self-timed monotonic logic progression utilizing vector logic variables, each of the vector logic variables defined by vector components on respective logic paths, each of the vector logic variables exhibiting an invalid state when all of said logic paths exhibit logic low, each of the vector logic variables exhibiting a unique one of a plurality of possible valid states when a subset of said logic paths exhibits logic high, the gate for deriving a sum output vector with three vector components and a carry output vector with two vector components from three input vectors including a first operand with three vector components, a second operand with three vector components, and a carry operand with two vector components, comprising: logic means comprising ten ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing ladder logic outputs; buffer means comprising ten inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said output vector, said inverting buffer mechanisms configured to maintain said vector components of said output vectors at logic low before receiving a ladder logic signal on said ladder logic outputs so that said output vectors exhibit said invalid state, sad inverting buffer mechanisms configured to receive said ladder logic signal on said ladder logic outputs and to invert said ladder logic signal to thereby derive said output vectors in said valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, sad arming mechanisms configured to precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components of said output vectors at logic low; and said logic means, said buffer means, and said arming means, in combination, adapted to perform said ternary addition operation on said input vectors to derive said output vectors.

Claim 60

A vector logic method for implementing a self-timed monotonic logic progression in a logic network, the method comprising the steps of: defining a vector logic variable by a plurality of vector components situated on logic paths of said logic network; and encoding timing information in said vector logic variable by defining said vector logic variable as invalid when all said vector components are concurrently inactive and by defining said vector logic variable as valid when a subset of said vector components are active, wherein said subset corresponding with each valid vector logic state is nonoverlapping relative to other subsets, and wherein said subset is greater than one.

Claim 61

A vector logic method for implementing a self-timed monotonic logic progression in a logic network, the method comprising the steps of: defining a vector logic variable by a plurality of vector components situated on logic paths of said logic network; and encoding timing information in said vector logic variable by defining said vector logic variable as invalid when all said vector components are concurrently inactive and by defining said vector logic variable as valid when a subset of said vector components are active, wherein said subset corresponding with each valid vector logic state is nonoverlapping relative to other subsets, and wherein said subset is greater than one.

Claim 62

The method of claim 49, wherein said logic network comprises a gate having a ladder logic connected to a plurality of gate inputs and to an inverting buffer mechanism, the inverting buffer mechanism for providing gate outputs after receipt of a ladder logic output, and an arming mechanism for periodically precharging the inverting buffer mechanism to drive said gate outputs to a logic low until said inverting buffer mechanism is triggered by said ladder logic.

Claim 63

The method of claim 49, wherein said logic network comprises a dynamic logic gate.

Claim 64

The method of claim 49, wherein said subset is two in number.

Claim 65

The method of claim 49, wherein said gate inputs number at least three.

Claim 66

The method of claim 49, further comprising the step of encoding more than one invalid logic state with said vector logic variable.

Claim 67

The method of claim 49, further comprising the step of encoding a non-Boolean logic variable with said vector logic variable.

Claim 68

The method of claim 49, further comprising the step of employing said logic gate in an adder logic circuit.

Claim 69

The method of claim 49, further comprising the step of employing said logic gate within a multiplier logic circuit.

Claim 70

A logic gate for performing an add predecoder logic operation with a self-timed monotonic logic progression utilizing vector logic variables, each-vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said logic means is configured so that said add predecoder logic operation is performed by said gate on said input vectors to derive said output vector.

Claim 71

A logic gate for performing an add predecoder logic operation with a self-timed monotonic logic progression utilizing vector logic variables, each-vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said logic means is configured so that said add predecoder logic operation is performed by said gate on said input vectors to derive said output vector.

Claim 72

A logic gate for performing a carry propagate logic operation with a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said logic means is configured so that said carry propagate logic operation is performed by said gate on said input vectors to derive said output vector.

Claim 73

A logic gate for performing a carry propagate logic operation with a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said logic means is configured so that said carry propagate logic operation is performed by said gate on said input vectors to derive said output vector.

Claim 74

A logic gate for performing an exclusive OR logic operation with a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said logic means is configured so that said exclusive OR logic operation is performed by said gate on said input vectors to derive said output vector.

Claim 75

A logic gate for performing an exclusive OR logic operation with a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said logic means is configured so that said exclusive OR logic operation is performed by said gate on said input vectors to derive said output vector.

Claim 76

A logic gate for performing a Y-encoder logic operation for Booth's algorithm using a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said logic means is configured so that said Y encoder logic operation for said Booth's algorithm is performed by said gate on said input vectors to derive said output vector.

Claim 77

A logic gate for performing a Y-encoder logic operation for Booth's algorithm using a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said logic means is configured so that said Y encoder logic operation for said Booth's algorithm is performed by said gate on said input vectors to derive said output vector.

Claim 78

A logic gate for performing a ternary addition operation with a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said logic means is configured so that said ternary addition operation is performed by said gate on said input vectors to derive said output vector.

Claim 79

A logic gate for performing a ternary addition operation with a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit logic low, each of said valid states exhibited when a subset of said logic paths exhibit logic high, and wherein said subset is nonoverlapping relative to other subsets corresponding with other valid states, the logic gate for deriving an output vector from input vectors, comprising: logic means comprising a plurality of ladder logics, said logic means for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic; buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logics, said inverting buffer mechanisms configured to output said vector components defining said output vector, said inverting buffer mechanisms configured to maintain said vector components at logic low before receiving said ladder logic output so that said output vector exhibits an invalid state, one of said inverting buffer mechanisms configured to receive said ladder logic output and invert said ladder logic output to thereby derive said output vector in a valid state; arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at logic low; and wherein said logic means is configured so that said ternary addition operation is performed by said gate on said input vectors to derive said output vector.