US4468575A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit in 2-phase MOS-technology
Assignee: US Philips Corp
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Filing: 1981-12-09
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Granted: 1984-08-28
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Expires: 2001-12-09
Abstract
Abstract In a logic circuit arrangement comprising a plurality of sticks formed by series arrangements of transistors which receive the signals to be processed a conductive stick not only has to discharge the output capacitance of the logic output but also other sticks which are not completely conductive, namely up to the first cut-off transistor. This may result in a very high capacitive load, which substantially reduces the maximum attainable switching speed. In accordance with the invention an additional transistor is arranged between each stick and the output of the entire logic circuit, which transistor receives a gate voltage such that current flow from the cut-off charged sticks via a conductive stick is prevented or delayed until the output signal of the logic circuit has assumed a value which unambiguously switches over the next output transistor. As a result of this, a conductive stick only has to discharge the output capacitance of the logic circuit arrangement, so that a substantially higher switching speed can be obtained.
Inventors
- 👤 Egon Mathes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
247 words
A logic circuit in two phase MOS technology comprising a plurality of logic elements, each of said plurality arranged to include a MOS sensing transistor and a series arrangement of MOS transistors, first means for applying signals to be processed to said series arrangements, second means for applying sensing clock signals to said sensing transistors, third means for applying a reference potential to one end of each of said series arrangements, fourth means for applying operating voltage to the opposite end of each of said series arrangement through a MOS charging transistor common to each of said series arrangements, said charging transistor receiving charging clock signals, said sensing transistor of each of said series arrangements and said charging transistor being alternatively conductive in time, said charging transistor having a main electrode connected to said series arrangements, fifth means for applying outputs of said series arrangements to a gate of at least one MOS output transistor, said MOS output transistor supplying unambiguous low signals when the output of said logic circuit carries a voltage between said operating voltage and a fraction thereof, and additional MOS transistors connected between each of said series arrangements and said MOS charging transistor, said additional MOS transistors having gate electrodes together receiving a signal such that each of said additional MOS transistors is cutoff for voltage values between said operating voltage and a voltage value lower than a fraction of voltage on said output at least during conductive phases of said sensing transistors.
Claim 2
Dependent Claim
247 words
A logic circuit in two phase MOS technology comprising a plurality of logic elements, each of said plurality arranged to include a MOS sensing transistor and a series arrangement of MOS transistors, first means for applying signals to be processed to said series arrangements, second means for applying sensing clock signals to said sensing transistors, third means for applying a reference potential to one end of each of said series arrangements, fourth means for applying operating voltage to the opposite end of each of said series arrangement through a MOS charging transistor common to each of said series arrangements, said charging transistor receiving charging clock signals, said sensing transistor of each of said series arrangements and said charging transistor being alternatively conductive in time, said charging transistor having a main electrode connected to said series arrangements, fifth means for applying outputs of said series arrangements to a gate of at least one MOS output transistor, said MOS output transistor supplying unambiguous low signals when the output of said logic circuit carries a voltage between said operating voltage and a fraction thereof, and additional MOS transistors connected between each of said series arrangements and said MOS charging transistor, said additional MOS transistors having gate electrodes together receiving a signal such that each of said additional MOS transistors is cutoff for voltage values between said operating voltage and a voltage value lower than a fraction of voltage on said output at least during conductive phases of said sensing transistors.
Claim 3
Dependent Claim
25 words
A logic circuit according to claim 1, wherein said additional MOS transistors control capacitive discharge of said series arrangements of MOS transistors by said signal.
Claim 4
Dependent Claim
16 words
A logic circuit according to claim 1, wherein said additional MOS transistors are enhancement type transistors.
Claim 5
Dependent Claim
60 words
A logic circuit according to claim 3, wherein said signal on said gate electrodes of said additional MOS transistors is a direct voltage having a value smaller than the sum of the lowest voltage on said MOS output transistors and the threshold voltage of said additional MOS transistors, said lowest voltage being a value for maintaining said unambiguous low signals.
Claim 6
Dependent Claim
25 words
A logic circuit according to claim 3, wherein said signal on said gate electrodes of said additional MOS transistors is equivalent to said operating voltage.
Claim 7
Dependent Claim
75 words
A logic circuit according to claim 3, wherein said signal on said gate electrodes of said additional MOS transistors is a clock signal having voltage values, when said sensing transistors conduct, smaller than the sum of the lowest voltage for which said output transistor supplies an unambiguous low signal and a threshhold voltage of said additional MOS transistors, said voltage values of said clock signal being greater at least when said MOS charging transistor conducts.
Claim 8
Dependent Claim
27 words
A logic circuit according to claim 6, wherein said voltage values of said clock signal is equal to said operating voltage when said MOS charging transistor conducts.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-28 | 1988-02-27 | 1988-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-28 | 1992-02-27 | 1992-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-28 | 1996-02-27 | 1996-08-28 | $7700.00 | Window Closed / Lapsed |