High speed multiphase gate

Claim 2

A high-speed gate having an output terminal and using a multiphase clock cycle, said gate comprising: a plurality of inverter stages each including a logic network having first and second terminals, said network being implemented by a plurality of field effect transistors connected between said two terminals, each of said inverter stages having an output; an output field effect transistor driver for each of said inverter stages connected between said output terminal and a multiphase clock signal, the gate electrodes of the field effect transistor drivers connected to the outputs of the inverter stages, said output terminal being common to the field effect transistor drivers; each inverter stage comprising a load field effect transistor connected between said first terminal of said logic network and a voltage source for becoming conductive during a first- and second-phase time of said multiphase clock cycle for providing a first voltage level to said first terminal of a logic network during said first-phase time, and an isolation field effect transistor connected between said first terminal and the gate electrode of the associated output field effect transistor driver for becoming conductive during a second- and third-phase time of said multiphase clock cycle for applying said first voltage level to said gate electrode during said second-phase time; said second terminal of each of said logic networks being connected to a voltage source for providing a first voltage level during said first- and second-phase times and a second voltage level at least during said third-phase time whereby, if the logic function of said logic network is true during said third-phase time, the first voltage level applied to the gate electrode of said output field effect transistor driver during said second-phase time is changed to said second voltage level for rendering the associated output field effect transistor driver nonconductive at least during a fourth-phase time of said multiphase clock cycle, said recited multiphase clock signal providing a first voltage level at least during said fourth-phase time whereby said output is set to said first voltage level during said fourth-phase time if any one of the logic functions is false during said third-phase time.

Claim 3

A high-speed gate combining a plurality of logic functions at a common output terminal using a multiphase clock cycle, said gate comprising: a plurality of inverter stages each including a logic network having first and second terminals, said logic network being implemented by a plurality of field effect transistors connected between said first and second terminals, each of said inverter stages having an output; an output field effect transistor driver for each of said inverter stages with the driver for at least one inverter and the driver for at least one other inverter being connected in electrical series between a multiphase clock signal and said output terminal, the gate electrodes of said field effect transistor drivers connected to the outputs of their associated inverter stages; each of said inverter stages comprising a load field effect transistor connected between a first terminal of the logic network for an inverter stage and a voltage source for providing a first voltage level to the first terminal of each logic network during a first-phase time of said multiphase clock signal and to the gate electrode of each output field effect transistor driver during a second-phase time of said multiphase clock cycle, and an isolation field effect transistor connected between said first terminal and the gate electrode of an associated driver for connecting said first voltage level to said gate electrode during said second-phase time of said multiphase clock cycle, said isolation field effect transistor remaining conductive during a third-phase of said multiphase clock cycle; the second terminal of each logic network being connected to a clock signal for providing a first voltage level to said second terminals during said first- and second-phase time and for providing a second voltage level to said second terminals at least during said third-phase time whereby the gate electrodes of said drivers are connected to said second voltage level during said third-phase time if the logic functions of said logic networks are true whereby, said output field effect transistor drivers are rendered conductive if the voltage level on the gate electrodes remains set to said first voltage level during a fourth-phase time of said multiphase clock cycle and are rendered nonconductive if the voltage on said gate electrodes is changed to said second voltage level during said fourth-phase time.

Claim 4

A high-speed gate combining a plurality of logic functions at a common output terminal using a multiphase clock cycle, said gate comprising: a plurality of inverter stages each including a logic network having first and second terminals, said logic network being implemented by a plurality of field effect transistors connected between said first and second terminals, each of said inverter stages having an output; an output field effect transistor driver for each of said inverter stages with the driver for at least one inverter and the driver for at least one other inverter being connected in electrical series between a multiphase clock signal and said output terminal, the gate electrodes of said field effect transistor drivers connected to the outputs of their associated inverter stages; each of said inverter stages comprising a load field effect transistor connected between a first terminal of the logic network for an inverter stage and a voltage source for providing a first voltage level to the first terminal of each logic network during a first-phase time of said multiphase clock signal and to the gate electrode of each output field effect transistor driver during a second-phase time of said multiphase clock cycle, and an isolation field effect transistor connected between said first terminal and the gate electrode of an associated driver for connecting said first voltage level to said gate electrode during said second-phase time of said multiphase clock cycle, said isolation field effect transistor remaining conductive during a third-phase of said multiphase clock cycle; the second terminal of each logic network being connected to a clock signal for providing a first voltage level to said second terminals during said first- and second-phase time and for providing a second voltage level to said second terminals at least during said third-phase time whereby the gate electrodes of said drivers are connected to said second voltage level during said third-phase time if the logic functions of said logic networks are true whereby, said output field effect transistor drivers are rendered conductive if the voltage level on the gate electrodes remains set to said first voltage level during a fourth-phase time of said multiphase clock cycle and are rendered nonconductive if the voltage on said gate electrodes is changed to said second voltage level during said fourth-phase time.