Logic full adder circuit

Claim 2

A logic full adder for adding two binary numbers a and b having n bits each, where n is equal to or greater than 2 including a plurality of single bit adders, each comprising: an inverting AND gate and inverting OR gate for receiving a pair of like bit numbers a i and b i and producing an inverted OR signal a i +b i and an inverted AND signal a i ·b i for each of said pairs of bit numbers; a summing circuit for producing a sum signal from each pair of said like bit numbers a i and b i comprising a logic gate which receives said like bit numbers a i , b i and said inverted AND signal a i ·b i , and forms on first and second outputs a first signal a i ·b i ·(a i +b i ), and a second signal a i ·b i ·(a i +b i ), respectively; a pair of electronic switches connected to receive said first and second signals, and operated in response to a carry signal c i , to supply either said first signal or said second signal to a first junction; and a carry look-ahead circuit for generating a carry look-ahead signal from said inverted OR signals a i +b i and said inverted AND signals a i ·b i produced by each of said pairs of bit numbers.

Claim 3

The logic full adder of claim 1 further comprising a carry signal circuit which includes a second pair of electronic switches receiving each pair of inverted OR signals a i +b i and inverted AND signals a i ·b i for supplying under control of said carry signal c i either said inverted OR signal or said inverted AND signal to a second junction.

Claim 4

A logic full-adder circuit as claimed in claim 2, which full-adder circuit is constructed with complementary insulated-gate field-effect transistors, the electronic switches together comprise four N-channel field-effect transistors, a first and a second transistor thereof connecting the second and the first output, respectively of the said logic gate, to the first junction, the third and the fourth transistor connecting the output of the inverting OR-gate and the output of the inverting AND-gate, respectively, to the second junction, the first and the third transistor being controlled by the carry signal c i and the second and the fourth transistor being controlled by an inverted carry signal c i .

Claim 5

A logic full-adder circuit as claimed in claim 3, further comprising, first and second P-channel field-effect transistors, which are controlled by the carry signal c i , connected in parallel with the second and the fourth transistors respectively.

Claim 6

A logic full-adder circuit as claimed in claim 3, wherein two series-connected inverters are connected to the second junction for producing on the outputs thereof a carry signal c i+1 and the inverted carry signal c i+1 hving the significance i+1, respectively.

Claim 7

A logic full-adder circuit as claimed in claims 3, 4 or 5, wherein each logic gate comprises: a serious connection of two P-channel transistors which receive the bit signals a i and b i , respectively, on their gate electrodes, a further P-channel transistor which is connected in parallel with the two P-channel transistors and whose gate electrode receives the inverted AND-signal a i ·b i , a parallel connection of two N-channel transistors which is connected in series with the parallel connection of the P-channel transistors forming said first output, the gate electrodes of said N-channel transistors receiving the bit signals a i and b i , respectively, and a further N-channel transistor which is connected in series with the two parallel-connected N-channel transistors and whose gate electrode receives the inverted AND-signal a i ·b i , the logic gate also comprising an inverter which is composed of a P- and an N-channel transistor and whose gate electrode is connected to the junction of said P- and N-channel transistors which forms the first output of the logic gate, the output of the inverter forming the second output of the logic gate.

Claim 8

A logic full-adder circuit as claimed in claim 1, wherein the carry look-ahead signal circuit comprises a first series connection of transistors, gate electrodes of which receive the AND-signals a i ·b i for each of the pairs of like bit numbers with an ascending order, the transistor whose gate electrode receives the AND-signal a 0 ·b 0 of lowest order 0 being connected in series with a carry transistor whose gate electrode receives the carry signal c 0 having the order 0, one transistor of a plurality of transistors being connected in parallel with each section of the series connection of the carry transistor and m further transistors from said first series connection, m assuming any value from 1 to n, the gate electrode of said one transistor receiving the OR-signal a m-1 + m31 1.

Claim 9

A logic full-adder circuit as claimed in claim 7, wherein the transistors which are connected in series and in parallel in the carry look-ahead signal circuit are N-channel field-effect transistors which are connected in series with a single P-channel field-effect transistor between two power supply terminals.