Parallel operating mode arithmetic logic unit apparatus

Claim 2

Arithmetic logic unit apparatus comprising, in combination: first signal input means; second signal input means; carry signal input means; AND, OR and Exclusive NOR (XNOR) gate means, connected to said first and second signal input means, for receiving first and second signals and providing parallel output AND, OR and XNOR signals responsive to said first and second signals; ripple carry means, connected to receive AND, OR and carry signals from said AND gate means, said OR gate means and said carry signal input means respectively, for controlling passage of AND and OR signals therethrough in response to the logic value of carry input control signals, said ripple carry means providing carry output signals; summing means, connected to said XNOR gate means and said carry signal input means, for receiving carry and XNOR signals whereby SUM output signal are provided in the form of carry and carry signals selectively passed by the logic value of said XNOR signals; and means, connected to said XNOR means, for providing XOR output signals.

Claim 5

The method of claim 2 comprising the additional step of: selecting one of said output signals in response to a control signal.

Claim 8

Arithmetic logic unit apparatus comprising, in combination: first signal input means; second signal input means; carry signal input means; AND, OR and Exclusive OR (XOR) gate means, connected to said first and second signal input means, for receiving first and second signals and providing parallel output AND, OR and XOR signals responsive to said first and second signals; ripple carry means, connected to receive AND, OR and carry signals from said AND gate means, said OR gate means and said carry signal input means respectively, for controlling passage of AND and OR signals therethrough in response to the logic value of carry input control signals, said ripple carry means providing carry output signals; summing means, connected to said XOR gate means and said carry signal input means, for receiving carry and XOR signals whereby SUM output signals are provided in the form of carry and carry signals selectively passed by the logic value of said XOR signals; and means, connected to said XOR means, for providing XNOR output signals.

Claim 9

Arithmetic logic unit apparatus comprising, in combination: first signal input means; second signal input means; carry signal input means; AND, OR and Exclusive OR (XOR) gate means, connected to said first and second signal input means, for receiving first and second signals and providing parallel output AND, OR and XOR signals responsive to said first and second signals; ripple carry means, connected to receive AND, OR and carry signals from said AND gate means, said OR gate means and said carry signal input means respectively, for controlling passage of AND and OR signals therethrough in response to the logic value of carry input control signals, said ripple carry means providing carry output signals; summing means, connected to said XOR gate means and said carry signal input means, for receiving carry and XOR signals whereby SUM output signals are provided in the form of carry and carry signals selectively passed by the logic value of said XOR signals; and means, connected to said XOR means, for providing XNOR output signals.

Claim 10

Arithmetic logic unit apparatus comprising, in combination: first signal input means; second signal input means; carry signal input means; AND, OR and an exclusive signal logic combination gate means, connected to said first and second signal input means, for receiving first and second signals and providing parallel output AND, OR and third signals responsive respectively to said first and second signals; ripple carry means, connected to receive AND, OR and carry signals from said AND gate means, said OR gate means and said carry signal input means respectively, for controlling passage of AND and OR signals therethrough in response to the logic value of carry input control signals, said ripple carry means providing carry output signals; summing means, connected to said exclusive signal logic combination gate means and said carry signal input means, for receiving carry and third signals whereby one of said carry output signals and third signals are selectively passed by the logic value of the other signal.

Claim 11

Arithmetic logic unit apparatus comprising, in combination: first signal input means; second signal input means; carry signal input means; AND, OR and an exclusive signal logic combination gate means, connected to said first and second signal input means, for receiving first and second signals and providing parallel output AND, OR and third signals responsive respectively to said first and second signals; ripple carry means, connected to receive AND, OR and carry signals from said AND gate means, said OR gate means and said carry signal input means respectively, for controlling passage of AND and OR signals therethrough in response to the logic value of carry input control signals, said ripple carry means providing carry output signals; summing means, connected to said exclusive signal logic combination gate means and said carry signal input means, for receiving carry and third signals whereby one of said carry output signals and third signals are selectively passed by the logic value of the other signal.

Claim 12

Apparatus as claimed in claim 6, wherein said exclusive signal logic combination gate means is an exclusive NOR gate means and said third signals are exclusive NOR signals.

Claim 13

Apparatus as claimed in claim 6, wherein said exclusive signal logic combination gate means is an exclusive OR gate means and said third signals are exclusive OR signals.

Claim 14

Apparatus as claimed in claim 6, wherein said summing means passes the third signals which are logically controlled by the carry signals.

Claim 15

Apparatus for decreasing throughput time in an arithmetic logic unit (ALU) relative to prior art approaches comprising, in combination: first signal input means for supplying first input signals; second signal input means for supplying second input signals; carry input means for supplying carry input signals from a previous stage of computation; AND gate means, OR gate means, and exclusive signal logic combination gate means for simultaneously ADDing, ORing, and exclusive logic combining said first and second input signals to provide AND, OR and third signals respectively; carry circuit means, including carry output means, connected to said AND gate means, OR gate means, and said carry input signal means, for logically passing the AND and OR signals in accordance with the logic value of said carry input signals, said carry circuit means providing carry output signals at said output means thereof; and SUM means, connected to said carry input means and to said exclusive signal logic combination gate means, for passing one of said carry input signals and said third signals in accordance with the logic value of the other of said carry input signals and said third signals to form SUM output signals.

Claim 16

Apparatus for decreasing throughput time in an arithmetic logic unit (ALU) relative to prior art approaches comprising, in combination: first signal input means for supplying first input signals; second signal input means for supplying second input signals; carry input means for supplying carry input signals from a previous stage of computation; AND gate means, OR gate means, and exclusive signal logic combination gate means for simultaneously ADDing, ORing, and exclusive logic combining said first and second input signals to provide AND, OR and third signals respectively; carry circuit means, including carry output means, connected to said AND gate means, OR gate means, and said carry input signal means, for logically passing the AND and OR signals in accordance with the logic value of said carry input signals, said carry circuit means providing carry output signals at said output means thereof; and SUM means, connected to said carry input means and to said exclusive signal logic combination gate means, for passing one of said carry input signals and said third signals in accordance with the logic value of the other of said carry input signals and said third signals to form SUM output signals.

Claim 17

Apparatus as claimed in claim 10 comprising, in addition: multiplexing means connected to receive said AND signals, said OR signals, said SUM signals and said third signal, said multiplexing means including control input means and ALU apparatus output signal means; and means for supplying selection control signals to said control input means of said multiplexing means for selecting one of the signals input to said multiplexing means as an output signal from the ALU apparatus.