Expandable arithmetic logic unit

Claim 1

An arithmetic logic unit (ALU) for performing binary and BCD arithmetic and a plurality of logic functions on at least first and second data input sets Ai and Bi where i is an integer which varies from 0 to n, comprising: selection means for enabling said ALU to perform a desired function, said selection means producting a plurality of enabling signals; first logic means coupled to said selection means and to said data input sets for generating propagate (Pi) and generate (Gi) signals informative to the existence of carry out signals which would result from the combination of bits of equal significance in said at least first and second data sets, said first logic means producing said propagate and generate signals in a first single stage of logic delay; second logic means coupled to said selection means and to said first logic means for producing group propagate and group generate signals informative of the existence of carry out signals which would result from the combination of predetermined subsets of equal significance of said at least first and second data sets, said second logic means producing said group propagate and group generate signals in a second single stage of logic delay; carry look-ahead means coupled to said selection means and to said first and second logic means for generating carry signals Ci in a third single stage of logic delay; third logic means coupled to said selection means and to said first logic mens for generating signals Hi representative of half-sums of corresponding bits in said at least first and second data sets, said third logic means producing said half-sums in said second stage of logic delay; and fourth logic means coupled to said selection means, to said third logic means and to said carry look-ahead means for combining said half sums Hi and said carry signals Ci to produce a desired ALU output in a fourth single stage of logic delay.