Inverter circuits using insulated gate field effect transistors

Claim 2

An inverter circuit comprising a complementary pair formed by first and second insulated gate field effect transistors connected in series across terminals of a power supply, an output terminal coupled to a junction point between said first and second transistors, a diode coupled between a control electrode of said first transistor and a power supply terminal associated therewith, said diode being poled to clamp said control electrode at a predetermined voltage relative to the voltage of the power supply terminal associated with said first transistor, an input terminal coupled to a control electrode of said second transistor, means including a capacitance means coupled between said control electrode of said first transistor and said input terminal for establishing a time constant at said control electrode of said first transistor, and means for applying to said input terminal an input control pulse which is shorter than said time constant, the capacitance value of said capacitance means being sufficiently larger than the internal capacitance of said first transistor so that a potential difference substantially equal to the amplitude of said input control pulse appears between said power supply terminal associated with said first transistor and the control electrode of said first transistor and the voltage at the control electrode of said first transistor becomes lower than the voltage of said power supply terminal associated with said first transistor to the extent that said first transistor may be turned on when said input control pulse goes from a high level to a low level.

Claim 3

The inverter of claim 1 wherein said established time constant is the RC time constant of said capacitance means coupled in series with a resistance means which is in turn coupled in parallel with said diode.

Claim 4

The inverter of claim 1 or claim 2 wherein said diode is a Zener diode.

Claim 5

The inverter of claim 3 further comprising a second Zener diode coupled to said control terminal of said second transistor.

Claim 6

The inverter of claim 1, further comprising a second diode coupled between the control electrode of said second transistor and the power supply terminal associated therewith, and means including a second capacitance means coupled between the control electrode of said second transistor and said input terminal for establishing a second time constant at the control electrode of said second transistor, said second capacitance means being sufficiently larger than the internal capacitance of said second transistor.

Claim 7

The inverter of claim 5 wherein said second time constant is the RC time constant of said second capacitance means and a second resistance means coupled between said second capacitance means and a power supply terminal associated with said second transistor.

Claim 8

The inverter of claim 5 further comprising a resistance means coupled between said control terminal of said second transistor and said power supply terminal associated with said second transistor.

Claim 9

The inverter of claim 1 or claim 5, further comprising means for independently applying input pulses to control electrodes of said first and second transistors, said input pulses having pulse periods which preclude a simultaneous switching one of the two transistors.

Claim 10

A plasma display panel comprising an X-Y matrix of dots arranged in columns and rows; column driver means for selectively energizing any predetermined ones of said columns; line driver means for selectively energizing any one of said rows, whereby the combination of the selective energization of said column and line driver means selects predetermined dots in said matrix; and inverter means individually associated with said column driver means and said line driver means, respectively, for energizing said driver means; each of said inverter means comprising a complementary pair formed by first and second insulated gate field effect transistors connected in series across terminals of a power supply; an output terminal coupled to a junction point between said first and second transistors; a diode coupled between a control electrode of said first transistor and a power supply terminal associated therewith, said diode being poled to clamp said control electrode at a predetermined voltage relative to the voltage of the power supply terminal associated with said first transistor; an input terminal coupled to a control electrode of said second transistor; means including a capacitance means coupled between said control electrode of said first transistor and said input terminal for establishing a time constant at said control electrode of said one transistor; and means for applying to said input terminal an input control pulse which is shorter than said time constant, the capacitance value of said capacitance means being sufficiently larger than the internal capacitance of said first transistor so that a potential difference substantially equal to the amplitude of said input control pulse appears between said power supply terminal associated with said first transistor and the control electrode of said first transistor and the voltage at the control electrode of said first transistor becomes lower than the voltage of said power supply terminal associated with said first transistor to the extent that said first transistor may be turned on when said input control pulse goes from a high level to a low level.

Claim 11

A plasma display panel comprising an X-Y matrix of dots arranged in columns and rows; column driver means for selectively energizing any predetermined ones of said columns; line driver means for selectively energizing any one of said rows, whereby the combination of the selective energization of said column and line driver means selects predetermined dots in said matrix; and inverter means individually associated with said column driver means and said line driver means, respectively, for energizing said driver means; each of said inverter means comprising a complementary pair formed by first and second insulated gate field effect transistors connected in series across terminals of a power supply; an output terminal coupled to a junction point between said first and second transistors; a diode coupled between a control electrode of said first transistor and a power supply terminal associated therewith, said diode being poled to clamp said control electrode at a predetermined voltage relative to the voltage of the power supply terminal associated with said first transistor; an input terminal coupled to a control electrode of said second transistor; means including a capacitance means coupled between said control electrode of said first transistor and said input terminal for establishing a time constant at said control electrode of said one transistor; and means for applying to said input terminal an input control pulse which is shorter than said time constant, the capacitance value of said capacitance means being sufficiently larger than the internal capacitance of said first transistor so that a potential difference substantially equal to the amplitude of said input control pulse appears between said power supply terminal associated with said first transistor and the control electrode of said first transistor and the voltage at the control electrode of said first transistor becomes lower than the voltage of said power supply terminal associated with said first transistor to the extent that said first transistor may be turned on when said input control pulse goes from a high level to a low level.

Claim 12

A plasma display panel comprising an X-Y matrix of data means arranged in rows and columns; column driver means for selectively energizing any preselected ones of said columns in said matrix; line driver means for selectively energizing any preselected one of said rows in said matrix; inverter means individually associated with each of said driver means for generating high voltage pulses for driving said driver means and thereby driving the rows and columns of said matrix, each of said inverter means comprising a pair of N- and P-type insulated gate field effect transistors coupled in series; an output terminal connected between drain electrodes of said transistors, for generating said high voltage pulses; a diode coupled between the source and gate electrodes of one of said transistors; a resistance means coupled to the gate of said one transistor, the other side of said resistance means being connected to either the source of said one transistor or to ground voltage; a capacitance means connected to the gate of said one transistor, means for applying to the other side of said capacitance means a low voltage pulse having a period which is shorter than the RC time constant of said capacitance means and said resistance means; means for applying a high voltage to the source of said one transistor; and means for applying to the gate of the other transistor a low voltage input signal; said capacitance means being sufficiently larger than the gate input capacitance of said one transistor so that a potential difference substantially equal to the amplitude of said low voltage pulse applied to said capacitance means appears between said source and gate of said one transistor whereby the voltage on the gate of said one transistor decreases to a level which is sufficiently lower than the voltage on the source of said one transistor to turn on said one transistor when said low voltage pulse applied to said capacitance means goes from a high level to a low level.

Claim 13

A plasma display panel comprising an X-Y matrix of data means arranged in rows and columns; column driver means for selectively energizing any preselected ones of said columns in said matrix; line driver means for selectively energizing any preselected one of said rows in said matrix; inverter means individually associated with each of said driver means for generating high voltage pulses for driving said driver means and thereby driving the rows and columns of said matrix, each of said inverter means comprising a pair of N- and P-type insulated gate field effect transistors coupled in series; an output terminal connected between drain electrodes of said transistors, for generating said high voltage pulses; a diode coupled between the source and gate electrodes of one of said transistors; a resistance means coupled to the gate of said one transistor, the other side of said resistance means being connected to either the source of said one transistor or to ground voltage; a capacitance means connected to the gate of said one transistor, means for applying to the other side of said capacitance means a low voltage pulse having a period which is shorter than the RC time constant of said capacitance means and said resistance means; means for applying a high voltage to the source of said one transistor; and means for applying to the gate of the other transistor a low voltage input signal; said capacitance means being sufficiently larger than the gate input capacitance of said one transistor so that a potential difference substantially equal to the amplitude of said low voltage pulse applied to said capacitance means appears between said source and gate of said one transistor whereby the voltage on the gate of said one transistor decreases to a level which is sufficiently lower than the voltage on the source of said one transistor to turn on said one transistor when said low voltage pulse applied to said capacitance means goes from a high level to a low level.

Claim 14

The inverter of claim 10 wherein said diode is a Zener diode poled to clamp said control electrode at a predetermined voltage relative to the voltage of the power supply terminal associated with said one transistor.

Claim 15

The inverter of claim 11 further comprising a second Zener diode coupled to the gate of said other transistor to protect an oxide film associated therewith.

Claim 16

A high voltage complementary insulated gate field effect transistor inverter circuit comprising, a first terminal connected to a high voltage power supply, a second terminal connected to a low voltage power supply, an output terminal for delivering either said high or low voltages, an input terminal, a P-channel insulated gate field effect transistor coupled across said first and output terminals, an N-channel insulated gate field effect transistor coupled across said second and output terminals, the gate electrode of said N-channel insulated gate field effect transistor being connected to said input terminal, a diode coupled across said first terminal and the gate electrode of said P-channel insulated gate field effect transistor, a resistor coupled across said first terminal and said gate electrode of said P-channel insulated gate field effect transistor, a capacitor coupled between said gate electrode of said P-channel insulated gate field effect transistor and the gate electrode of said N-channel insulated gate field effect transistor, and means for applying to said input terminal a low voltage pulse having a period which is shorter than the RC time constant of said capacitor and said resistor, the negative side of said diode being connected to said first terminal so that the voltage on the gate electrode of said P-channel insulated gate field effect transistor is kept below the voltage on said first terminal when said low voltage pulse goes from a low level to a high level, the capacitance of said capacitor being sufficiently larger than the gate input capacitance of said P-channel insulated gate field effect transistor so that a potential at the gate electrode of said P-channel insulated gate field effect transistor becomes lower than the potential at said first terminal to the extent that said P-channel insulated gate field effect transistor is turned on when said low voltage pulse goes from said high level to said low level.

Claim 17

A high voltage complementary insulated gate field effect transistor inverter circuit comprising, a first terminal connected to a high voltage power supply, a second terminal connected to a low voltage power supply, an output terminal for delivering either said high or low voltages, an input terminal, a P-channel insulated gate field effect transistor coupled across said first and output terminals, an N-channel insulated gate field effect transistor coupled across said second and output terminals, the gate electrode of said N-channel insulated gate field effect transistor being connected to said input terminal, a diode coupled across said first terminal and the gate electrode of said P-channel insulated gate field effect transistor, a resistor coupled across said first terminal and said gate electrode of said P-channel insulated gate field effect transistor, a capacitor coupled between said gate electrode of said P-channel insulated gate field effect transistor and the gate electrode of said N-channel insulated gate field effect transistor, and means for applying to said input terminal a low voltage pulse having a period which is shorter than the RC time constant of said capacitor and said resistor, the negative side of said diode being connected to said first terminal so that the voltage on the gate electrode of said P-channel insulated gate field effect transistor is kept below the voltage on said first terminal when said low voltage pulse goes from a low level to a high level, the capacitance of said capacitor being sufficiently larger than the gate input capacitance of said P-channel insulated gate field effect transistor so that a potential at the gate electrode of said P-channel insulated gate field effect transistor becomes lower than the potential at said first terminal to the extent that said P-channel insulated gate field effect transistor is turned on when said low voltage pulse goes from said high level to said low level.

Claim 18

An inverter circuit comprising a pair of N-and-P type insulated gate field effect transistors coupled in series, an output terminal connected between drain electrodes of said transistors, a diode coupled between the source and gate electrodes of one of said transistors, an input terminal connected to the gate electrode of the other transistor, means including a capacitance means connected to the gate electrode of said one transistor for establishing a time constant, means for applying to the other side of said capacitance means a low voltage pulse having a period which is shorter than said time constant, said low voltage pulse being applied through either said input terminal or another individual input terminal connected to said capacitor, said diode being poled to clamp the gate electrode of said one transistor at a predetermined voltage relative to the voltage of a power supply terminal associated with said one transistor when said low voltage pulse goes from a low level to a high level, the capacitance of said capacitance means being sufficiently larger than the gate input capacitance of said one transistor so that most of said low voltage pulse appears between the gate and the source of said one transistor due to the capacitive division of said capacitance means and said gate input capacitance which are connected in series with each other between said power supply terminal and either said input terminal or said another individual input terminal, whereby the voltage on the gate of said one transistor is lower than the voltage at the source of said one transistor so as to turn on said one transistor when said low voltage pulse goes from said high level to said low level.

Claim 19

An inverter circuit comprising a pair of N-and-P type insulated gate field effect transistors coupled in series, an output terminal connected between drain electrodes of said transistors, a diode coupled between the source and gate electrodes of one of said transistors, an input terminal connected to the gate electrode of the other transistor, means including a capacitance means connected to the gate electrode of said one transistor for establishing a time constant, means for applying to the other side of said capacitance means a low voltage pulse having a period which is shorter than said time constant, said low voltage pulse being applied through either said input terminal or another individual input terminal connected to said capacitor, said diode being poled to clamp the gate electrode of said one transistor at a predetermined voltage relative to the voltage of a power supply terminal associated with said one transistor when said low voltage pulse goes from a low level to a high level, the capacitance of said capacitance means being sufficiently larger than the gate input capacitance of said one transistor so that most of said low voltage pulse appears between the gate and the source of said one transistor due to the capacitive division of said capacitance means and said gate input capacitance which are connected in series with each other between said power supply terminal and either said input terminal or said another individual input terminal, whereby the voltage on the gate of said one transistor is lower than the voltage at the source of said one transistor so as to turn on said one transistor when said low voltage pulse goes from said high level to said low level.

Claim 20

An inverter circuit comprising a pair of N-and-P type insulated gate field effect transistors coupled in series, an output terminal connected between drain electrodes of said transistors, a diode coupled between the source and gate electrodes of one of said transistors, said diode being poled to clamp said gate electrode at a predetermined voltage relative to the voltage of a power supply terminal associated with said one transistor, an input terminal connected to the gate electrode of the other transistor, a resistor coupled to the gate of said one transistor, the other side of said resistor being connected to ground voltage, a capacitor having a capacitance which is larger than the gate input capacitance of said one transistor, said capacitor being connected to the gate electrode of said one transistor, means for applying to the other side of said capacitor a low voltage pulse having a period which is shorter than the RC time constant of said capacitor and said resistor, through either said input terminal or another individual input terminal connected to said capacitor.

Claim 21

An inverter circuit comprising a pair of N-and-P type insulated gate field effect transistors coupled in series, an output terminal connected between drain electrodes of said transistors, a diode coupled between the source and gate electrodes of one of said transistors, said diode being poled to clamp said gate electrode at a predetermined voltage relative to the voltage of a power supply terminal associated with said one transistor, an input terminal connected to the gate electrode of the other transistor, a resistor coupled to the gate of said one transistor, the other side of said resistor being connected to ground voltage, a capacitor having a capacitance which is larger than the gate input capacitance of said one transistor, said capacitor being connected to the gate electrode of said one transistor, means for applying to the other side of said capacitor a low voltage pulse having a period which is shorter than the RC time constant of said capacitor and said resistor, through either said input terminal or another individual input terminal connected to said capacitor.

Claim 22

The inverter circuit of either claim 14 or claim 15 and means for applying said low voltage pulse through said input terminal.

Claim 23

The inverter circuit of either claim 14 or claim 15 and another input terminal connected to said capacitor, and means for applying said low voltage pulse through said other input terminal.

Claim 24

An inverter circuit comprising a complementary pair of insulated gate field effect transistors connected in series across terminals of a power supply, electronic switch means coupled between a control electrode of one of said pair of transistors and a power supply terminal associated therewith, means including a capacitance means connected at its one terminal to said control electrode of said one transistor for establishing a time constant at said control electrode of said one transistor, said capacitance means being larger than the internal capacitance of said one transistor, means for applying to the other terminal of said capacitance means a control pulse which is shorter than said time constant, and means for applying to the control electrode of said other transistor an input control pulse, the relationship between said control pulse and input control pulse being such that said one transistor is turned on to its conducting state while said other transistor is in its nonconducting state.

Claim 25

An inverter circuit comprising a complementary pair of insulated gate field effect transistors connected in series across terminals of a power supply, electronic switch means coupled between a control electrode of one of said pair of transistors and a power supply terminal associated therewith, means including a capacitance means connected at its one terminal to said control electrode of said one transistor for establishing a time constant at said control electrode of said one transistor, said capacitance means being larger than the internal capacitance of said one transistor, means for applying to the other terminal of said capacitance means a control pulse which is shorter than said time constant, and means for applying to the control electrode of said other transistor an input control pulse, the relationship between said control pulse and input control pulse being such that said one transistor is turned on to its conducting state while said other transistor is in its nonconducting state.