US4284905A
Expired / Lapsed
US
⏱️ 0.0 years remaining
IGFET Bootstrap circuit
Assignee: AT&T Inc
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Filing: 1979-05-31
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Granted: 1981-08-18
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Expires: 1999-05-31
Abstract
Abstract An improved IGFET bootstrap driver circuit capable of driving a load impedance to substantially full VDD power supply voltage and holding the load at that voltage for an indefinite period of time. The circuit includes a load transistor, a feedback capacitor connected between the source and gate electrodes of the load transistor, a fix valued resistor connected between the gate electrode of the load transistor and an on-chip bias voltage generating circuit for providing a bias voltage greater than VDD+VT. The resistor and the bias voltage generating circuit provide sufficient current to replenish the charge lost from the feedback capacitor through junction leakage currents in the driver circuit. The resistor is of a sufficiently high value such that the current drain from the generating circuit is insignificantly small in comparison to the current drain from the VDD power supply. The improved circuit also permits the load transistor to be switched "on" or "off" by an externally applied signal.
Inventors
- 👤 Walter Rosenzweig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:10
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714; H03K19/0175; H03K19/0185; H03K19/018507
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
185 words
An IGFET driver circuit comprising a first voltage supply terminal adapted to carry a first bias voltage, an output node, a control node, a first IGFET having its channel coupled between the first voltage supply terminal and the output node, the gate of the first IGFET being coupled to the control node, a second IGFET having its channel coupled between the first voltage supply terminal and the control node, capacitance means coupled between the output node and the control node, a second voltage supply terminal adapted to carry a second bias voltage, at least one input terminal for receiving an input signal, switching means coupled between the output node and the second voltage supply terminal, the switching means responsive to the input signal at the input terminal for providing a conducting path between the output node and the second voltage supply terminal, characterized in that there are included a third voltage supply terminal adapted to carry a third bias voltage of greater magnitude than the first bias voltage, and substantially fixed value resistance means coupled between the third voltage supply terminal and the control node.
Claim 2
Dependent Claim
185 words
An IGFET driver circuit comprising a first voltage supply terminal adapted to carry a first bias voltage, an output node, a control node, a first IGFET having its channel coupled between the first voltage supply terminal and the output node, the gate of the first IGFET being coupled to the control node, a second IGFET having its channel coupled between the first voltage supply terminal and the control node, capacitance means coupled between the output node and the control node, a second voltage supply terminal adapted to carry a second bias voltage, at least one input terminal for receiving an input signal, switching means coupled between the output node and the second voltage supply terminal, the switching means responsive to the input signal at the input terminal for providing a conducting path between the output node and the second voltage supply terminal, characterized in that there are included a third voltage supply terminal adapted to carry a third bias voltage of greater magnitude than the first bias voltage, and substantially fixed value resistance means coupled between the third voltage supply terminal and the control node.
Claim 3
Dependent Claim
39 words
An IGFET driver circuit as recited in claim 1 wherein the switching means comprise a third IGFET having its channel coupled between the output node and the second voltage supply terminal and its gate coupled to the input terminal.
Claim 4
Dependent Claim
22 words
An IGFET driver circuit as recited in claim 2 further characterized in that the resistance means comprise one or more polysilicon resistors.
Claim 5
Dependent Claim
61 words
An IGFET driver circuit as recited in claim 3 further characterized in that there is included a bias voltage generating circuit situated on the same substrate as the driver circuit, the generating circuit for providing the third bias voltage having a magnitude greater than that of the sum of the first bias voltage and the threshold voltage of the first EGFET.
Claim 6
Dependent Claim
207 words
An IGFET driver circuit comprising a first voltage supply terminal adapted to carry a first bias voltage, an output node, a control node, a first IGFET having its channel coupled between the first voltage supply terminal and the output node, the gate of the first IGFET being coupled to the control node, capacitance means coupled between the output node and the control node, a second voltage supply terminal adapted to carry a second bias voltage, at least one input terminal for receiving an input signal, switching means coupled between the output node and the second voltage supply terminal, the switching means responsive to the input signal at the input terminal for providing a conducting path between the output node and the second voltage supply terminal. characterized in that there are included a third voltage supply terminal adapted to carry a third bias voltage of greater magnitude than the first bias voltage, a clock input node for receiving a clock signal, a second IGFET having its channel coupled between the control node and the clock input node, the gate of the second IGFET being coupled to the first voltage supply terminal, and substantially fixed value resistance means coupled between the third voltage supply terminal and the control node.
Claim 7
Dependent Claim
207 words
An IGFET driver circuit comprising a first voltage supply terminal adapted to carry a first bias voltage, an output node, a control node, a first IGFET having its channel coupled between the first voltage supply terminal and the output node, the gate of the first IGFET being coupled to the control node, capacitance means coupled between the output node and the control node, a second voltage supply terminal adapted to carry a second bias voltage, at least one input terminal for receiving an input signal, switching means coupled between the output node and the second voltage supply terminal, the switching means responsive to the input signal at the input terminal for providing a conducting path between the output node and the second voltage supply terminal. characterized in that there are included a third voltage supply terminal adapted to carry a third bias voltage of greater magnitude than the first bias voltage, a clock input node for receiving a clock signal, a second IGFET having its channel coupled between the control node and the clock input node, the gate of the second IGFET being coupled to the first voltage supply terminal, and substantially fixed value resistance means coupled between the third voltage supply terminal and the control node.
Claim 8
Dependent Claim
43 words
An IGFET driver circuit as recited in claim 5 wherein the switching means comprise a third IGFET having its channel coupled between the second voltage supply terminal and the output node, the gate of the third IGFET being coupled to the input terminal.
Claim 9
Dependent Claim
22 words
An IGFET driver circuit as recited in claim 6 further characterized in that the resistance means comprise one or more polysilicon resistors.
Claim 10
Dependent Claim
61 words
An IGFET driver circuit as recited in claim 7 further characterized in that there is included a bias voltage generating circuit situated on the same substrate as the driver circuit, the generating circuit for providing the second bias voltage having a magnitude greater than that of the sum of the first bias voltage and the threshold voltage of the first IGFET.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-08-17 | 1985-02-16 | 1985-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-08-17 | 1989-02-16 | 1989-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-08-17 | 1993-02-16 | 1993-08-18 | $7700.00 | Window Closed / Lapsed |