Dynamic logic circuits using transistors having differing threshold voltages

Claim 2

A logic circuit, comprising: a source of a precharge voltage; a clock signal generator producing a clock signal having a precharge phase and an evaluate phase; a precharge node a precharge device coupled to the source of the precharge voltage, the clock generator and the precharge node operable to precharge the precharge node to the precharge voltage during the precharge phase of the clock signal; and a conditional series discharge path connected to said precharge node, receiving first and second input signals and operable to conditionally couple said precharge node to a voltage different than the precharge voltage dependent upon a logic state of the respective first and second input signals, wherein said conditional series discharge path comprises: a low threshold voltage transistor having a first threshold voltage, a gate receiving the first input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the first input signal; and a high threshold voltage transistor having a second threshold voltage higher in magnitude than the first threshold voltage, a gate receiving the second input signal and conditionally providing a conductive discharge path along said conditional series discharge path dependent upon the logic state of the second input signal, wherein the logic state of the second input signal is disabling during the precharge phase such that said conductive path of said high threshold voltage transistor is not conducting during the precharge phase.

Claim 3

The logic circuit of claim 1 wherein said low threshold voltage transistor comprises a first low threshold voltage transistor, and wherein said conditional series discharge path further comprises a second low threshold voltage transistor having the first threshold voltage, a gate receiving a third input signal and conditionally providing a conduction path along said series discharge path dependent upon a logic state of the third input signal.

Claim 4

The logic circuit of claim 2 wherein said conditional paths of said first and second low threshold voltage transistors are connected to form a series connection, and further comprising a third low threshold voltage transistor having a gate receiving a fourth input signal and conditionally providing a conductive path connected in parallel to said series connection dependent upon a logic state of the fourth input signal, and wherein said third low threshold voltage transistor has the first threshold voltage.

Claim 5

The logic circuit of claim 3 wherein each of said first, second, and third low threshold voltage transistors comprises an n-channel transistor.

Claim 6

The logic circuit of claim 1 and wherein: the precharge device comprises of a p-channel transistor having a source connected to the source of the precharge voltage, a drain connected to said precharge node, and a gate connected to receive the clock signal such that a conduction path of said p-channel transistor is conducting during the precharge phase; and said high threshold voltage transistor comprises an n-channel transistor having a source connected to a source of the voltage lower than the precharge voltage and a gate coupled to receive the second input signal such that said conductive path of said n-channel transistor is not conducting during the precharge phase.

Claim 7

The logic circuit of claim 5: wherein the gate of said p-channel transistor is coupled to receive a disabling signal during the evaluate phase such that said conduction path of said p-channel transistor is not conducting during the evaluate phase; and wherein the gate of said n-channel transistor is coupled to receive an enabling signal during the evaluate phase such that said conductive path of said n-channel transistor is conducting during the evaluate phase.

Claim 8

The logic circuit of claim 5 wherein the second input signal is the clock signal such that when the clock signal is low, the clock signal is enabling to said p-channel transistor and disabling to said n-channel transistor.

Claim 9

The logic circuit of claim 1: wherein the second input signal connected to the gate of the high threshold voltage transistor is provided by a gated clock signal having a logic state during the precharge phase such that said high threshold voltage transistor is disabled during the precharge phase such that said conductive path of said high threshold voltage transistor is not conducting during the precharge phase and having an optional logic state during said evaluate phase such that said high threshold voltage transistor is optionally enabled during the evaluate phase such that said conductive path of said high threshold voltage transistor is conditionally conducting during the evaluate phase depending upon the logic state of the second input signal; and wherein the first input signal connected to the gate of said low threshold voltage transistor is output by a static circuit.

Claim 10

The logic circuit of claim 1 wherein the second input signal connected to the gate of said high threshold voltage transistor is provided by an output of a dynamic logic circuit such that said high threshold voltage transistor is disabled during the precharge phase such that said conductive path of said high threshold voltage transistor is not conducting during the precharge phase, said output of the dynamic logic circuit having an optional logic state during said evaluate phase such that said high threshold voltage transistor is optionally enabled during the evaluate phase such that said conductive path of said high threshold voltage transistor is conditionally conducting during the evaluate phase depending upon the logic state of the second input signal.

Claim 11

The logic circuit of claim 9: wherein said high threshold voltage transistor comprises a first high threshold voltage transistor; wherein said conductive paths of said low threshold voltage transistor and said first high threshold voltage transistor are connected to form a series connection; and wherein said dynamic logic circuit further comprises a second high threshold voltage transistor providing a conductive path along said conditional series discharge path connected in parallel to said series connection, wherein said second high threshold voltage transistor has the second threshold voltage and a third input signal connected to a gate of said second high threshold voltage transistor is provided by an output of the dynamic logic circuit such that said second high threshold voltage transistor is disabled during the precharge phase such that said conductive path of said second high threshold voltage transistor is not conducting during the precharge phase.

Claim 12

The logic circuit of claim 1 wherein said conditional series discharge path further comprises an additional transistor connected as an inverter, wherein said additional transistor has a gate connected for receiving an inverter input signal, a source connected to ground and a drain for presenting a signal complementary to said inverter input signal, wherein said additional transistor has the second threshold voltage.

Claim 13

The logic circuit of claim 11 and wherein said precharge node comprises a first precharge node and wherein the precharge voltage comprises a first precharge voltage, and further comprising: a source of a second precharge voltage; a second precharge node a second precharge device coupled to the source of the second precharge voltage, the clock generator and the second precharge node operable to precharge the second precharge node to the second precharge voltage during the precharge phase of the clock signal; a second conditional discharge path connected to said second precharge node and operable to conditionally couple said second precharge node to a voltage different than the second precharge voltage during the evaluate phase; and wherein an input of said inverter is connected to said second precharge node.

Claim 14

The logic circuit of claim 1 wherein said conditional discharge path comprises a first conditional series discharge path, wherein said low threshold voltage transistor comprises a first low threshold voltage transistor, and wherein said high threshold voltage transistor comprises a first high threshold voltage transistor, and further comprising: a second conditional series discharge path connected to said precharge node, receiving third and fourth input signals and operable to conditionally couple said precharge node to a voltage different than the precharge voltage dependent upon a logic state of the respective third and fourth input signals, wherein said second conditional series discharge path comprises: a second low threshold voltage transistor having the first threshold voltage, a gate receiving the third input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon the logic state of the third input signal; and a second high threshold voltage transistor having the second threshold voltage, a gate receiving the fourth input signal and conditionally providing a conductive discharge path along said second conditional series discharge path dependent upon the logic state of the fourth input signal, wherein the logic state of the fourth input signal is disabling during the precharge phase such that said conductive path of said second high threshold voltage transistor is not conducting during the precharge phase.

Claim 15

The logic circuit of claim 1 wherein said high threshold voltage transistor comprises a transistor connected as an inverter, wherein said high threshold voltage transistor has a gate connected for receiving an inverter input signal, a source connected to ground and a drain for presenting a signal complementary to said invert input signal, wherein the inverter input signal is provided by an output of a dynamic logic circuit such that said high threshold voltage transistor is disabled during the precharge phase such that said conductive path of said high threshold voltage transistor is not conducting during the precharge phase.

Claim 16

The logic circuit of claim 1 wherein said high threshold voltage transistor comprises a transistor connected as an inverter, wherein said high threshold voltage transistor has a gate connected for receiving an inverter input signal, a source connected to ground and a drain for presenting a signal complementary to said invert input signal, wherein the inverter input signal is provided by an output of a static logic circuit which is gated such that said high threshold voltage transistor is disabled during the precharge phase such that said conductive path of said high threshold voltage transistor is not conducting during the precharge phase.

Claim 17

The logic circuit of claim 1 wherein said conditional discharge path comprises a first conditional series discharge path, wherein said low threshold voltage transistor comprises a first low threshold voltage transistor, and wherein said high threshold voltage transistor comprises a first high threshold voltage transistor, and further comprising: a second conditional series discharge path connected to said precharge node, receiving third and fourth input signals and operable to conditionally couple said precharge node to a voltage different than the precharge voltage dependent upon a logic state of the respective third and fourth input signals, wherein said second conditional series discharge path comprises: a second low threshold voltage transistor having the first threshold voltage, a gate receiving the third input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon the logic state of the third input signal; and a second high threshold voltage transistor having the second threshold voltage, a gate receiving the fourth input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon the logic state of the fourth input signal, wherein the logic state of the fourth input signal is disabling during the precharge phase such that said conductive path of said second high threshold voltage transistor is not conducting during the precharge phase.

Claim 18

The logic circuit of claim 16: wherein each of said second and fourth input signals is provided by outputs of respective dynamic logic circuits such that said first and second high threshold voltage transistors are disabled during the precharge phase such that the conductive paths of said first and second high threshold voltage transistors are not conducting during the precharge phase; wherein a first node exists between said first low threshold voltage transistor and said first high threshold voltage transistor; wherein a second node exists between said second low threshold voltage transistor and said second high threshold voltage transistor; and wherein said first node is connected to said second node.

Claim 19

The logic circuit of claim 1 wherein said precharge node comprises a first precharge node, wherein the precharge voltage comprises a first precharge voltage, and wherein each of said low threshold and high threshold voltage transistors comprises a first conductivity type, and further comprising: a source of a second precharge voltage; a second precharge node; a second precharge device coupled to the clock generator and the second precharge node operable to precharge the second precharge node to the second precharge voltage during the precharge phase of the clock signal; and a second conditional series discharge path connected to said second precharge node, receiving third and fourth input signals and operable to conditionally couple said second precharge node to a voltage different than the second precharge voltage dependent upon a logic state of the respective third and fourth input signals, wherein said second conditional series discharge path comprises: a second low threshold voltage transistor of a second conductivity type, having the first threshold voltage corresponding to the second conductivity type, a gate receiving the third input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon the logic state of the third input signal; and a second high threshold voltage transistor of the second conductivity type having the second threshold voltage corresponding to the second conductivity type higher in magnitude than the first threshold voltage corresponding to the second conductivity type, a gate receiving the fourth input signal and conditionally providing a conductive discharge path along said second conditional series discharge path dependent upon the logic state of the fourth input signal, wherein the logic state of the fourth input signal is disabling during the precharge phase such that said conductive path of said second high threshold voltage transistor of the second conductivity type is not conducting during the precharge phase; wherein the voltage at the first precharge node provides a data input to one of said second low threshold voltage transistor of the second conductivity type and said second high threshold voltage transistor of the second conductivity type.

Claim 20

The logic circuit of claim 1 and wherein the precharge device comprises of a p-channel transistor having a source connected to the source of the precharge voltage, a drain connected to said precharge node, and a gate connected to receive the clock signal such that a conduction path of said p-channel transistor is conducting during the precharge phase.

Claim 21

The logic circuit of claim 1 and further comprising an inverter having an input coupled to said precharge node.

Claim 22

The logic circuit of claim 20 and further comprising a p-channel transistor having a source connected to the source of the precharge voltage, a drain connected to said precharge node, and a gate connected to an output of said inverter.

Claim 23

The logic circuit of claim 1 wherein each of said low threshold voltage transistor and said high threshold voltage transistor comprises an n-channel transistor.

Claim 24

The logic circuit of claim 1: wherein said conditional series discharge path comprises a first conditional series discharge path; wherein said low threshold voltage transistor comprises a first low threshold voltage transistor; the logic circuit further comprising a second conditional series discharge path connected to said precharge node, receiving third and fourth input signals and operable to conditionally couple said precharge node to a voltage different than the precharge voltage dependent upon a logic state of the respective third and fourth input signal; wherein said second conditional series discharge path comprises: a second low threshold voltage transistor having the first threshold voltage, a gate receiving the third input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon the logic state of the third input signal, wherein said third input signal is disabling during the precharge phase such that said conductive path of said second low threshold voltage transistor is not conducting during the precharge phase; and a third low threshold voltage transistor having the first threshold voltage, a gate receiving the fourth input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon the logic state of the fourth input signal, wherein the logic state of the fourth input signal is disabling during the precharge phase such that said conductive path of said third low threshold voltage transistor is not conducting during the precharge phase.

Claim 25

The logic circuit of claim 1 wherein said precharge node comprises a first precharge node, and further comprising a second precharge node coupled to be precharged to the precharge voltage during the precharge phase and operable to be discharged during the evaluate phase, wherein only one of said first and second precharge nodes is discharged during the evaluate phase.

Claim 26

The logic circuit of claim 24 and further comprising a conditional series discharge path coupled to said second precharge node, wherein said conditional series discharge path coupled to said second precharge node further comprises said high threshold voltage transistor.

Claim 27

The logic circuit of claim 24 and further comprising: a second conditional series discharge path connected to said second precharge node, receiving third and fourth input signals and operable to conditionally couple said second precharge node to a voltage different than the precharge voltage dependent upon a logic state of the respective third and fourth input signals, wherein said second conditional series discharge path comprises: a second low threshold voltage transistor having the first threshold voltage, a gate receiving the third input signal and conditionally providing a conductive path along said second conditional series discharge path connected to said second precharge node dependent upon the logic state of the third input signal; and a second high threshold voltage transistor having the second threshold voltage higher in magnitude than the first threshold voltage, a gate receiving the fourth input signal and conditionally providing a conductive discharge path along said second conditional series discharge path dependent upon the logic state of the fourth input signal, wherein the logic state of the fourth input signal is disabling during the precharge phase such that said conductive path of said second high threshold voltage transistor is not conducting during the precharge phase.

Claim 28

The logic circuit of claim 1: wherein said precharge node and said conditional series discharge path and said precharge device are included in a first phase dynamic logic circuit comprising one or more stages; wherein each of said one or more dynamic logic circuit stages of said first phase dynamic logic circuit comprises said precharge node and said conditional discharge path; wherein each precharge node of each of said one or more dynamic logic stages is further coupled to a precharge device which when conducting couples said each precharge node of said each stage to the precharge voltage during said precharge phase; and further comprising a second phase dynamic logic circuit comprising one or more dynamic logic stages, wherein each of said one or more dynamic logic stages of said second phase dynamic logic circuit comprises: a precharge node; a conditional series discharge path connected to said precharge node of said second phase dynamic logic circuit and operable to conditionally couple said precharge node of said second phase dynamic logic circuit to a voltage different than the precharge voltage; and a precharge device coupled to the source of the precharge voltage and said precharge node of said second phase dynamic logic circuit which when conducting couples said precharge node of said second phase dynamic logic circuit to the precharge voltage during said precharge phase; wherein each of said dynamic logic stages of said first and second phase dynamic logic circuits further comprises an output for presenting a logic value responsive to the voltage at said precharge node of each of said first and second phase dynamic logic circuits; and further comprising control circuitry for controlling at least one of said dynamic logic stages of said first and second phase dynamic logic circuits as a storing stage such that said conditional series discharge path and said precharge device of each of said first and second phase dynamic logic circuits are not concurrently conducting during a predetermined time and such that the logic value is maintained at said output, wherein the predetermined time is equal to or greater than a time period equal to said evaluate phase plus said precharge phase.

Claim 29

The logic circuit of claim 1 wherein said low threshold voltage transistor is formed using a first implantation step and wherein said high threshold voltage transistor is formed using a second implantation step at a time different than said first implantation step.

Claim 30

The logic circuit of claim 1 wherein each of said low threshold voltage transistor and said high threshold voltage transistor comprises a silicon-on-insulator transistor.

Claim 31

The logic circuit of claim 29 wherein said low threshold voltage transistor comprises a body connection, and wherein said body connection floats.

Claim 32

The logic circuit of claim 29 wherein said high threshold voltage transistor comprises a body connection and a gate, and wherein said body connection is connected to said gate.

Claim 33

The logic circuit of claim 29 wherein said high threshold voltage transistor is an n-channel transistor comprising a body connection and a source, and wherein said body connection is connected to said source.

Claim 34

The logic circuit of claim 29 wherein said high threshold voltage transistor is an n-channel transistor comprising a body connection, and wherein said body connection is connected to ground.

Claim 35

The logic circuit of claim 29 wherein said high threshold voltage transistor is an n-channel transistor comprising a body connection, and wherein said body connection is connected to said precharge voltage.