US5572151A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pass transistor type selector circuit and digital logic circuit
Assignee: Hitachi Ltd
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Filing: 1995-08-07
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Granted: 1996-11-05
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Expires: 2015-08-07
Abstract
Abstract A pass transistor type selector circuit comprises a control signal supplying circuit for supplying a pair of control signals of opposite phases to the respective gate electrodes of a pair of nMOS transistors of a selecting circuit. The control signal supplying circuit includes a control signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal is low level. The control signal interrupting means is provided with a discharging means for discharging high-level one of the gate electrodes of the nMOS transistors of the signal selecting circuit while the clock signal is low level. The discharging means comprises two nMOS transistors, each connected between the respective gate electrodes of the nMOS transistors of the signal selecting circuit and a grounding terminal.
Inventors
- 👤 Makoto Hanawa
- 👤 Kenji Kaneko
- 👤 Noriyasu Ido
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:17
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/509; G06F7/60; G06F7/607; H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
192 words
A pass transistor type selector circuit comprising: a signal selecting circuit composed of a pair of signal selecting nMOS transistors whose drain electrodes are commonly connected so as to form an output terminal, and also including a pMOS transistor, wherein said pMOS transistor is connected between the output terminal of the signal selecting circuit and a power supply terminal, and wherein a gate electrode of said pMOS transistor is connected to an output terminal of an inverter connected to the output terminal of the signal selecting circuit; a control signal generating circuit for generating a pair of control signals of opposite phases; a control signal supplying circuit for supplying the control signals to the respective gate electrodes of the nMOS transistors of said signal selecting circuit; an input signal supplying circuit for supplying input signals to the respective source electrodes of the nMOS transistors of said signal selecting circuit; and said control signal supplying circuit including a control signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal level is low.
Claim 2
Dependent Claim
192 words
A pass transistor type selector circuit comprising: a signal selecting circuit composed of a pair of signal selecting nMOS transistors whose drain electrodes are commonly connected so as to form an output terminal, and also including a pMOS transistor, wherein said pMOS transistor is connected between the output terminal of the signal selecting circuit and a power supply terminal, and wherein a gate electrode of said pMOS transistor is connected to an output terminal of an inverter connected to the output terminal of the signal selecting circuit; a control signal generating circuit for generating a pair of control signals of opposite phases; a control signal supplying circuit for supplying the control signals to the respective gate electrodes of the nMOS transistors of said signal selecting circuit; an input signal supplying circuit for supplying input signals to the respective source electrodes of the nMOS transistors of said signal selecting circuit; and said control signal supplying circuit including a control signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal level is low.
Claim 3
Dependent Claim
156 words
A pass transistor type selector circuit comprising: a signal selecting circuit composed of a pair of signal selecting nMOS transistors whose drain electrodes are commonly connected so as to form an output terminal, a control signal generating circuit for generating a pair of control signals of opposite phases, a control signal supplying circuit for supplying the control signals to the respective gate electrodes of the nMOS transistors of said signal selecting circuit, an input signal supplying circuit for supplying input signals to the respective source electrodes of the nMOS transistors of said signal selecting circuit, said control signal supplying circuit including a control signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal level is low, wherein said control signal supplying circuit and said control signal generating circuit is composed of a domino logic circuit.
Claim 4
Dependent Claim
156 words
A pass transistor type selector circuit comprising: a signal selecting circuit composed of a pair of signal selecting nMOS transistors whose drain electrodes are commonly connected so as to form an output terminal, a control signal generating circuit for generating a pair of control signals of opposite phases, a control signal supplying circuit for supplying the control signals to the respective gate electrodes of the nMOS transistors of said signal selecting circuit, an input signal supplying circuit for supplying input signals to the respective source electrodes of the nMOS transistors of said signal selecting circuit, said control signal supplying circuit including a control signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal level is low, wherein said control signal supplying circuit and said control signal generating circuit is composed of a domino logic circuit.
Claim 5
Dependent Claim
68 words
A pass transistor type selector circuit according to claim 1, wherein said control signal interrupting means comprises a charging means for charging an output terminal of the control signal generating circuit while the clock signal level is low, and a discharging means for discharging at least high-level one of the gate electrodes of the nMOS transistors of said signal selecting circuit while the clock signal level is low.
Claim 6
Dependent Claim
36 words
A pass transistor type selector circuit according to claim 3, wherein said charging means comprises two pMOS transistors, each connected between the respective output terminals of said control signal generating circuit and the power supply terminal.
Claim 7
Dependent Claim
38 words
A pass transistor type selector circuit according to claim 3, wherein said discharging means comprises two nMOS transistors, each connected between the respective gate electrodes of the nMOS transistors of said signal selecting circuit and a grounding terminal.
Claim 8
Dependent Claim
40 words
A pass transistor type selector circuit according to claim 5, wherein each of said discharging nMOS transistors forms at least one element of an inverter circuit for inverting the phase of the output signal of said control signal generating circuit.
Claim 9
Dependent Claim
63 words
A pass transistor type selector circuit according to claim 1, further comprising a voltage compensating pMOS transistor connected between the output terminal of said signal selecting circuit and the power supply terminal, which becomes conductive in synchronism with the clock signal while the clock signal level is low, so as to restore the potential of the output terminal to a power source voltage.
Claim 10
Dependent Claim
150 words
A pass transistor type selector circuit comprising: a signal selecting circuit composed of a pair of signal selecting nMOS transistors whose drain electrodes are commonly connected so as to form an output terminal, a control signal generating circuit for generating a pair of control signals of opposite phases, a control signal supplying circuit for supplying the control signals to the respective gate electrodes of the nMOS transistors of said signal selecting circuit, an input signal supplying circuit for supplying input signals to the respective source electrodes of the nMOS transistors of said signal selecting circuit, said control signal supplying circuit including a control signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal level is low, wherein said input signal supplying circuit is composed of a dynamic logic circuit.
Claim 11
Dependent Claim
150 words
A pass transistor type selector circuit comprising: a signal selecting circuit composed of a pair of signal selecting nMOS transistors whose drain electrodes are commonly connected so as to form an output terminal, a control signal generating circuit for generating a pair of control signals of opposite phases, a control signal supplying circuit for supplying the control signals to the respective gate electrodes of the nMOS transistors of said signal selecting circuit, an input signal supplying circuit for supplying input signals to the respective source electrodes of the nMOS transistors of said signal selecting circuit, said control signal supplying circuit including a control signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal level is low, wherein said input signal supplying circuit is composed of a dynamic logic circuit.
Claim 12
Dependent Claim
148 words
A pass transistor type logic circuit composed of a plurality of pass transistor type selector circuits, each comprising: a signal selecting circuit composed of a pair of signal selecting nMOS transistors whose drain electrodes are commonly connected so as to form an output terminal; a control signal generating circuit for generating a pair of control signals of opposite phases; a control signal supplying circuit for supplying the control signals to the respective gate electrodes of the nMOS transistors of said signal selecting circuit; an input signal supplying circuit for supplying input signals to the respective source electrodes of the nMOS transistors of said signal selecting circuit; and said control signal supplying circuit including a signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal level is low.
Claim 13
Dependent Claim
148 words
A pass transistor type logic circuit composed of a plurality of pass transistor type selector circuits, each comprising: a signal selecting circuit composed of a pair of signal selecting nMOS transistors whose drain electrodes are commonly connected so as to form an output terminal; a control signal generating circuit for generating a pair of control signals of opposite phases; a control signal supplying circuit for supplying the control signals to the respective gate electrodes of the nMOS transistors of said signal selecting circuit; an input signal supplying circuit for supplying input signals to the respective source electrodes of the nMOS transistors of said signal selecting circuit; and said control signal supplying circuit including a signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal level is low.
Claim 14
Dependent Claim
68 words
A pass transistor type selector circuit according to claim 2, wherein said control signal interrupting means comprises a charging means for charging an output terminal of the control signal generating circuit while the clock signal level is low, and a discharging means for discharging at least high-level one of the gate electrodes of the nMOS transistors of said signal selecting circuit while the clock signal level is low.
Claim 15
Dependent Claim
36 words
A pass transistor type selector circuit according to claim 10, wherein said charging means comprises two pMOS transistors, each connected between the respective output terminals of said control signal generating circuit and the power supply terminal.
Claim 16
Dependent Claim
38 words
A pass transistor type selector circuit according to claim 10, wherein said discharging means comprises two nMOS transistors, each connected between the respective gate electrodes of the nMOS transistors of said signal selecting circuit and a grounding terminal.
Claim 17
Dependent Claim
40 words
A pass transistor type selector circuit according to claim 12, wherein each of said discharging nMOS transistors forms at least one element of an inverter circuit for inverting the phase of the output signal of said control signal generating circuit.
Claim 18
Dependent Claim
68 words
A pass transistor type selector circuit according to claim 8, wherein said control signal interrupting means comprises a charging means for charging an output terminal of the control signal generating circuit while the clock signal level is low, and a discharging means for discharging at least high-level one of the gate electrodes of the nMOS transistors of said signal selecting circuit while the clock signal level is low.
Claim 19
Dependent Claim
36 words
A pass transistor type selector circuit according to claim 14, wherein said charging means comprises two pMOS transistors, each connected between the respective output terminals of said control signal generating circuit and the power supply terminal.
Claim 20
Dependent Claim
38 words
A pass transistor type selector circuit according to claim 14, wherein said discharging means comprises two nMOS transistors, each connected between the respective gate electrodes of the nMOS transistors of said signal selecting circuit and a grounding terminal.
Claim 21
Dependent Claim
40 words
A pass transistor type selector circuit according to claim 16, wherein each of said discharging nMOS transistors forms at least one element of an inverter circuit for inverting the phase of the output signal of said control signal generating circuit.
Claim 22
Dependent Claim
63 words
A pass transistor type selector circuit according to claim 8, further comprising a voltage compensating pMOS transistor connected between the output terminal of said signal selecting circuit and the power supply terminal, which becomes conductive in synchronism with the clock signal while the clock signal level is low, so as to restore the potential of the output terminal to a power source voltage.
References Cited (Backward Citations)
US4577124A
Cited
US5015581A
Cited
US5059828A
Cited
JPH03157723A
Cited
US5418480A
Cited
US5399921A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |