Logic cell using only two N type transistors for generating each logic function

Claim 1

A logic cell, comprising: first, second and third inputs for receiving first, second and third input signals, respectively; first and second inverters coupled to the first and second inputs for producing first and second inverted input signals, respectively; a plurality of pairs of NMOS transistors, each NMOS transistor having a gate electrode, an input electrode and an output electrode, the gate electrode of one NMOS transistor of each said pair being coupled for directly receiving the second input signal and the other NMOS transistor of each said pair being coupled for receiving the second inverted input signal, the output electrodes of each said pair being connected together so that each pair of NMOS transistors has a common output, each input electrode of the NMOS transistors being coupled in a predetermined manner for receiving one of the first, second, inverted first and inverted second input signals for producing a different logical output signal on the respective common outputs of the NMOS transistor pairs; and a further pair of NMOS transistors arranged to form a 2 to 1 multiplexor having a control input constituting the third input for receiving the third input signal, the 2 to 1 multiplexor having inputs coupled for receiving the first and second input signals and an output, the 2 to 1 multiplexor producing one of the first and second input signals on its output in response to the third input signal.