US4633220A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Decoder using pass-transistor networks
Assignee: AMI Semiconductor Inc
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Filing: 1984-11-29
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Granted: 1986-12-30
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Expires: 2004-11-29
Abstract
Abstract A matrix comprised of pass transistor cells (81 through 96) forms an address decoder circuit (80). By using pass transistor cells in a matrix format, a decoder which consumes a minimum of power and which may be constructed using a minimum of allotted space in an integrated circuit is achieved.
Inventors
- 👤 Patrick A. Burgess
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 02:17
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/14; H03M7/20; H03M7/22; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
211 words
A digital decoder circuit comprising: a plurality of N input terminals for receiving N binary input signals, where N is a positive integer; a plurality of 2 N output terminals for providing a selected one of 2 N decoded output signals in response to said input signals; 2 M pass transistor AND gate cells having 2 M output leads, where M is a positive integer less than N, for decoding M of said N input signals to provide 2 M output signals on said 2 M output leads; 2 L pass transistor AND gate cells having 2 L output leads, where L is equal to N minus M, for decoding the L input signals of said N input signals not decoded by said 2 M pass transistor AND gate cells, to provide 2 L output signals on said 2 L output leads; and a 2 M by 2 L matrix of pass transistor AND gate cells having 2 M input leads connected to said 2 M output leads of said 2 M AND gate pass transistor cells, having 2 L input leads connected to said 2 L output leads of said 2 L pass transistor AND gate cells, and having 2 N output leads connected to said 2 N output terminals.
Claim 2
Dependent Claim
211 words
A digital decoder circuit comprising: a plurality of N input terminals for receiving N binary input signals, where N is a positive integer; a plurality of 2 N output terminals for providing a selected one of 2 N decoded output signals in response to said input signals; 2 M pass transistor AND gate cells having 2 M output leads, where M is a positive integer less than N, for decoding M of said N input signals to provide 2 M output signals on said 2 M output leads; 2 L pass transistor AND gate cells having 2 L output leads, where L is equal to N minus M, for decoding the L input signals of said N input signals not decoded by said 2 M pass transistor AND gate cells, to provide 2 L output signals on said 2 L output leads; and a 2 M by 2 L matrix of pass transistor AND gate cells having 2 M input leads connected to said 2 M output leads of said 2 M AND gate pass transistor cells, having 2 L input leads connected to said 2 L output leads of said 2 L pass transistor AND gate cells, and having 2 N output leads connected to said 2 N output terminals.
Claim 3
Dependent Claim
27 words
A digital decoder circuit as in claim 1 which further comprises an additional 2 N output terminal for providing the inverse of 2 N decoded output signals.
Claim 4
Dependent Claim
122 words
A digital decoder circuit as in claim 1 wherein at least one of said pass transistor AND gate cells comprises: a first input terminal for receiving a first input signal; PG,10 a second input terminal for receiving a second input signal; a third input terminal for receiving a third input signal which is the inverse of said second input signal; a fourth input terminal for receiving a reference voltage; an output terminal for providing an output signal; first switch means connected between said first input terminal and said output terminal, said first switch means controlled by second signal; and second switch means connected between said output terminal and said reference voltage, said second switch means being controlled by said third input signal.
Claim 5
Dependent Claim
112 words
A digital decoder circuit as in claim 1 wherein at least one of said first pass transistor AND gate cells comprises: a plurality of input terminals for receiving a plurality of input signals; an output terminal; a first plurality of switch means connected in series between a first reference voltage and said output terminal, each said first plurality of switch means being controlled by a unique one of said plurality of input signals; and a second plurality of switch means connected in parallel between said output terminal and a second reference voltage, each of said second plurality of switch means being controlled by a unique one of said plurality of input signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |