US4566064A
Expired / Lapsed
US
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Combinational logic structure using PASS transistors
Assignee: AMI Semiconductor Inc
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Filing: 1982-12-08
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Granted: 1986-01-21
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Expires: 2002-12-08
Abstract
Abstract PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a CONTROL signal applied to the transistor thereby to generate an output function related to the input function. In general, the input function comprises less than all of a set of input variables and the CONTROL function comprises one or more of the remainder of the set of input variables.
Inventors
- 👤 Sterling Whitaker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:44
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/503; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/20; H03K19/21; H03K19/215; H03K23/00; H03M; H03M11/00; H03M11/02; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4816
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
300 words
The method of constructing a logic circuit to represent a given logical function, said circuit using as its basic element the PASS transistor, said PASS transistor having an input lead, an output lead and a control lead controlled by a control function, said method comprising; establishing a first truth table of the desired logic function, said truth table depicting the state of the first output variable or variables for each state of the input variables; said step of establishing said first truth table including entering into said first truth table for each input state the input variables which, when passed to the output lead of a PASS transistor, yield the desired output variable or variables, said input variables comprising the PASS function for that state; establishing a plurality of second truth tables, each said second truth table having fewer variables than said first truth table, each said second truth table depicting one or more of a plurality of second output variables; said step of establishing said second truth table including, for each said second truth table, entering the PASS function for each state of the input variables into an associated modified Karnaugh map wherein each state of the modified Karnaugh map contains the particular input variables which yield the desired output variable, said particular input variables being called the PASS function for that state of input variables; identifying the identical PASS variables in each PASS function for each state of input variables such that every state has at least one PASS variable identified; identifying a control function among the input variables which is independent of the identical PASS variables previously identified, for controlling said control lead of said PASS transistor; and constructing a logic circuit using said PASS transistors in accordance with said identified PASS variables and said control function.
Claim 2
Independent Claim
300 words
The method of constructing a logic circuit to represent a given logical function, said circuit using as its basic element the PASS transistor, said PASS transistor having an input lead, an output lead and a control lead controlled by a control function, said method comprising; establishing a first truth table of the desired logic function, said truth table depicting the state of the first output variable or variables for each state of the input variables; said step of establishing said first truth table including entering into said first truth table for each input state the input variables which, when passed to the output lead of a PASS transistor, yield the desired output variable or variables, said input variables comprising the PASS function for that state; establishing a plurality of second truth tables, each said second truth table having fewer variables than said first truth table, each said second truth table depicting one or more of a plurality of second output variables; said step of establishing said second truth table including, for each said second truth table, entering the PASS function for each state of the input variables into an associated modified Karnaugh map wherein each state of the modified Karnaugh map contains the particular input variables which yield the desired output variable, said particular input variables being called the PASS function for that state of input variables; identifying the identical PASS variables in each PASS function for each state of input variables such that every state has at least one PASS variable identified; identifying a control function among the input variables which is independent of the identical PASS variables previously identified, for controlling said control lead of said PASS transistor; and constructing a logic circuit using said PASS transistors in accordance with said identified PASS variables and said control function.
Claim 3
Dependent Claim
80 words
The method of claim 1 wherein said step of identifying a control function comprises: using the identities that a PASS transistor which has a CONTROL function identical to its PASS function passes a high level signal when made conductive by the CONTROL function; and a PASS transistor which has a CONTROL function the inverse of its PASS function passes a low level signal when made conductive by the CONTROL function, to make the PASS function independent of the CONTROL variables.
Claim 4
Dependent Claim
31 words
The method of claim 2 including the additional steps of drawing a plurality of PASS transistor networks; and combining said plurality of PASS transistor networks into a single PASS transistor network.
Claim 5
Independent Claim
288 words
The method of constructing a logic circuit to represent a given logical function, said circuit using as its basic element the PASS transistor, said PASS transistor having an input lead, an output lead and a control lead controlled by a control function, said method comprising; establishing a first truth table of the desired logic function, said truth table depicting the state of the first output variable or variables for each state of the input variables; said step of establishing said first truth table including entering into said first truth table for each input state the input variables which, when passed to the output lead of a PASS transistor, yield the desired output variable or variables, said input variables comprising the PASS function for that state; establishing a plurality of second truth tables, each said second truth table having fewer variables than said first truth table, each said second truth table depicting one or more of a plurality of second output variables; said step of establishing said second truth table including, entering into each said second truth table for each input state the input variables which, when passed to the output lead of a PASS transistor, yield the desired output variable or variables for that truth table, said input variables comprising the PASS function for that state; identifying identical PASS variables in each PASS function for each state of input variables such that every state has at least one PASS variable identified; identifying a control function among the input variables which is independent of the identical PASS variables previously identified, for controlling said control lead of said PASS transistor; and constructing a logic circuit using said PASS transistors in accordance with said identified PASS variables and said control function.
Claim 6
Independent Claim
288 words
The method of constructing a logic circuit to represent a given logical function, said circuit using as its basic element the PASS transistor, said PASS transistor having an input lead, an output lead and a control lead controlled by a control function, said method comprising; establishing a first truth table of the desired logic function, said truth table depicting the state of the first output variable or variables for each state of the input variables; said step of establishing said first truth table including entering into said first truth table for each input state the input variables which, when passed to the output lead of a PASS transistor, yield the desired output variable or variables, said input variables comprising the PASS function for that state; establishing a plurality of second truth tables, each said second truth table having fewer variables than said first truth table, each said second truth table depicting one or more of a plurality of second output variables; said step of establishing said second truth table including, entering into each said second truth table for each input state the input variables which, when passed to the output lead of a PASS transistor, yield the desired output variable or variables for that truth table, said input variables comprising the PASS function for that state; identifying identical PASS variables in each PASS function for each state of input variables such that every state has at least one PASS variable identified; identifying a control function among the input variables which is independent of the identical PASS variables previously identified, for controlling said control lead of said PASS transistor; and constructing a logic circuit using said PASS transistors in accordance with said identified PASS variables and said control function.
Claim 7
Dependent Claim
80 words
The method of claim 4 wherein said step of identifying a control function comprises: using the identities that a PASS transistor which has a CONTROL function identical to its PASS function passes a high level signal when made conductive by the CONTROL function and a PASS transistor which has a CONTROL function the inverse of its PASS function passes a low level signal when made conductive by the CONTROL function, to make the PASS function independent of the CONTROL variables.
Claim 8
Dependent Claim
15 words
The method of claim 5 including the additional step of drawing the PASS transistor network.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-20 | 1989-07-22 | 1990-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-20 | 1993-07-22 | 1994-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-20 | 1997-07-22 | 1998-01-21 | $7700.00 | Window Closed / Lapsed |