Semiconductor memory decoder with nonselected row line hold down

Claim 2

In a semiconductor memory having an array of row lines, a decoder circuit comprising: a row driver transistor for each of said row lines; means for decoding an address signal for rendering conductive a selected one of said row driver transistors; means responsive to said address signal for rendering conductive the row driver transistor for the adjacent row line on either side of the row line corresponding to said selected row driver transistor; means responsive to said address signal for generating a first row driver signal for transmission through said selected row driver transistor to charge the row line connected thereto; and means responsive to said address signal for generating a second row driver signal for transmission through the row driver transistors for said adjacent row lines to affirmatively hold said adjacent row lines to a low voltage state.

Claim 3

The decoder circuit recited in claim 1 wherein said means for decoding comprises: an OR gate having a plurality of input terminals connected respectively to receive a first set of address bits selected from said address, and having an output terminal which is driven to a high voltage state when said OR gate is not selected by said first set of address bits and said OR gate output terminal is held at a low voltage state when said OR gate is selected by said first set of address bits; an inverter having an input terminal and an output terminal, the input terminal thereof connected to the output terminal of said OR gate; a pass transistor for each said row driver transistor, each pass transistor connected to the output of said inverter and the corresponding row driver transistor; and means for decoding a second set of address bits for rendering conductive the one of said pass transistors connected to the row driver transistor selected by said second set of address bits.

Claim 4

The decoder circuit recited in claim 1 wherein said means for rendering conductive comprises: means for precharging to a high voltage state each of the gate terminals of said row driver transistors; and means responsive to said address signal for trapping said high voltage state on the gate terminals of the row driver transistor on each side of the row driver transistor selected by said address signal.

Claim 5

In a semiconductor memory having an array of row lines, a decoder circuit comprising: a row driver transistor for each of said row lines; means for decoding an address signal for rendering conductive a selected one of said row driver transistors; means responsive to said address signal for rendering conducting every other row driver transistors in said array to include the row driver transistor on each side of said selected row driver transistor; means responsive to said address signal for generating a first row driver signal for transmission through said selected row driver transistor to charge the row line connected thereto; and means responsive to said address signal for generating a second row driver signal for transmission through said every other row driver transistors to affirmatively hold the row line connected thereto to a low voltage state.

Claim 6

In a semiconductor memory having an array of row lines, a decoder circuit comprising: a row driver transistor for each of said row lines; means for decoding an address signal for rendering conductive a selected one of said row driver transistors; means responsive to said address signal for rendering conducting every other row driver transistors in said array to include the row driver transistor on each side of said selected row driver transistor; means responsive to said address signal for generating a first row driver signal for transmission through said selected row driver transistor to charge the row line connected thereto; and means responsive to said address signal for generating a second row driver signal for transmission through said every other row driver transistors to affirmatively hold the row line connected thereto to a low voltage state.

Claim 7

In a semiconductor memory where a multi-bit address is decoded to charge one of a plurality of row lines for accessing memory cells connected to the charged row line, a circuit comprising: means responsive to a precharge signal for charging a first node to a first state, said first node corresponding to a group of said row lines; means responsive to a first set of address bits selected from said address for driving said first node to a second state when said first set of address bits does not select said group of row lines; means responsive to a second set of address bits selected from said address for generating a row driver signal for each of the row lines within said group and for driving to a high voltage state the one of said row driver signals selected by said second set of address bits; means for driving to a low voltage state the row driver signals for the row line on each side of the row line selected by said second set of address bits; a second node for each of said row lines within said group of row lines; means for connecting said first node to each of said second nodes upon receipt of a precharge signal for charging said second nodes to said first state; means responsive to said second set of address bits for connecting to said first node the second nodes corresponding to the row lines selected by said second set of address bits and for isolating from said first node the second nodes corresponding to the row lines not selected by said second set of address bits; and means for coupling each of said row driver signals to the corresponding row line when the corresponding second node is charged to said first state.

Claim 8

In a semiconductor memory where a multi-bit address is decoded to charge one of a plurality of row lines for accessing memory cells connected to the charged row line, a circuit comprising: means responsive to a precharge signal for charging a first node to a first state, said first node corresponding to a group of said row lines; means responsive to a first set of address bits selected from said address for driving said first node to a second state when said first set of address bits does not select said group of row lines; means responsive to a second set of address bits selected from said address for generating a row driver signal for each of the row lines within said group and for driving to a high voltage state the one of said row driver signals selected by said second set of address bits; means for driving to a low voltage state the row driver signals for the row line on each side of the row line selected by said second set of address bits; a second node for each of said row lines within said group of row lines; means for connecting said first node to each of said second nodes upon receipt of a precharge signal for charging said second nodes to said first state; means responsive to said second set of address bits for connecting to said first node the second nodes corresponding to the row lines selected by said second set of address bits and for isolating from said first node the second nodes corresponding to the row lines not selected by said second set of address bits; and means for coupling each of said row driver signals to the corresponding row line when the corresponding second node is charged to said first state.

Claim 9

In a semiconductor memory where a multi-bit address is decoded to charge a selected one of a plurality of row lines for accessing memory cells connected to the selected row line, a circuit comprising: a plurality of input transistors, the gate terminal of each input transistor connected to receive a respective bit of said address, the drain terminals of said input transistor connected to a positive power terminal and the source terminals of said input transistor connected to a first node; a first transistor having the drain terminal thereof connected to said first node, the source terminal thereof connected to a common node and the gate terminal thereof connected to receive a precharge signal; a second transistor having the drain terminal thereof connected to said power terminal, the gate terminal thereof connected to receive said precharge signal and the source terminal thereof connected to a second node; a third transistor having the gate terminal thereof connected to said first node, the drain terminal thereof connected to said second node and the source terminal thereof connected to said common node; a fourth transistor corresponding to a first one of said row lines within a pair of said row lines, said fourth transistor having the drain terminal thereof connected to said second node, the source terminal thereof connected to a third node and the gate terminal thereof connected to receive a CT0 signal; a fifth transistor corresponding to the second one of said row lines in said pair of row lines, said fifth transistor having the drain terminal thereof connected to said second node, the source terminal thereof connected to a fourth node and the gate terminal thereof connected to receive CT1 signal; means responsive to a given bit of said address for generating said CT0 signal; means responsive to said given bit for generating said CT1 signal; a first row driver transistor having the gate terminal thereof connected to said third node, the source terminal thereof connected to said first one of said row lines and the drain terminal thereof connected to receive an RD0 signal; a second row driver transistor having the gate terminal thereof connected to said fourth node, the source terminal thereof connected to said second one of said row lines and the drain terminal thereof connected to receive a RD1 signal; means responsive to said given address bit for generating said RD0 signal; and means responsive to said given address bit for generating said RD1 signal.

Claim 10

In a semiconductor memory where a multi-bit address is decoded to charge a selected one of a plurality of row lines for accessing memory cells connected to the selected row line, a circuit comprising: a plurality of input transistors, the gate terminal of each input transistor connected to receive a respective bit of said address, the drain terminals of said input transistor connected to a positive power terminal and the source terminals of said input transistor connected to a first node; a first transistor having the drain terminal thereof connected to said first node, the source terminal thereof connected to a common node and the gate terminal thereof connected to receive a precharge signal; a second transistor having the drain terminal thereof connected to said power terminal, the gate terminal thereof connected to receive said precharge signal and the source terminal thereof connected to a second node; a third transistor having the gate terminal thereof connected to said first node, the drain terminal thereof connected to said second node and the source terminal thereof connected to said common node; a fourth transistor corresponding to a first one of said row lines within a pair of said row lines, said fourth transistor having the drain terminal thereof connected to said second node, the source terminal thereof connected to a third node and the gate terminal thereof connected to receive a CT0 signal; a fifth transistor corresponding to the second one of said row lines in said pair of row lines, said fifth transistor having the drain terminal thereof connected to said second node, the source terminal thereof connected to a fourth node and the gate terminal thereof connected to receive CT1 signal; means responsive to a given bit of said address for generating said CT0 signal; means responsive to said given bit for generating said CT1 signal; a first row driver transistor having the gate terminal thereof connected to said third node, the source terminal thereof connected to said first one of said row lines and the drain terminal thereof connected to receive an RD0 signal; a second row driver transistor having the gate terminal thereof connected to said fourth node, the source terminal thereof connected to said second one of said row lines and the drain terminal thereof connected to receive a RD1 signal; means responsive to said given address bit for generating said RD0 signal; and means responsive to said given address bit for generating said RD1 signal.

Claim 11

In a semiconductor memory having an array of row lines, a method for charging a row line selected by a multi-bit memory address for accessing memory cells on the selected row line while holding certain nonselected row lines at ground, the method comprising the steps of: decoding the memory address and rendering conductive a row driver transistor connected to the selected row line; decoding a set of address bits selected from said memory address and rendering conductive the row driver transistor for the row line on each side of the selected row line; generating a first row driver signal having a high voltage state and transmitting said first row driver signal through said row driver transistor connected to said selected row line for charging said selected row line; and generating a second row driver signal having a low voltage state and transmitting said second row driver signal through said row driver transistors connected to the row line on each side of the selected row line for holding the row line on each side of the selected row line at ground.

Claim 12

In a semiconductor memory having an array of row lines, a method for charging a row line selected by a multi-bit memory address for accessing memory cells on the selected row line while holding certain nonselected row lines at ground, the method comprising the steps of: decoding the memory address and rendering conductive a row driver transistor connected to the selected row line; decoding a set of address bits selected from said memory address and rendering conductive the row driver transistor for the row line on each side of the selected row line; generating a first row driver signal having a high voltage state and transmitting said first row driver signal through said row driver transistor connected to said selected row line for charging said selected row line; and generating a second row driver signal having a low voltage state and transmitting said second row driver signal through said row driver transistors connected to the row line on each side of the selected row line for holding the row line on each side of the selected row line at ground.

Claim 13

In a semiconductor memory having an array of row lines, a method for charging a row line selected by a multi-bit memory address for accessing memory cells on the selected row line while holding certain nonselected row lines at ground, the method comprising the steps of: decoding the memory address and rendering conductive a row driver transistor connected to the selected row line; decoding a set of address bits selected from said memory address and rendering conductive the row driver transistors for every other row lines in said array to include the row line on each side of the selected row line; generating a first row driver signal having a high voltage state and transmitting said first row driver signal through said row driver transistor connected to said selected row line for charging said selected row line; and generating a second row driver signal having a low voltage state and transmitting said second row driver signal through said row driver transistor for every other row line for holding said every other row line at ground.

Claim 14

In a semiconductor memory having an array of row lines, a method for charging a row line selected by a multi-bit memory address for accessing memory cells on the selected row line while holding certain nonselected row lines at ground, the method comprising the steps of: decoding the memory address and rendering conductive a row driver transistor connected to the selected row line; decoding a set of address bits selected from said memory address and rendering conductive the row driver transistors for every other row lines in said array to include the row line on each side of the selected row line; generating a first row driver signal having a high voltage state and transmitting said first row driver signal through said row driver transistor connected to said selected row line for charging said selected row line; and generating a second row driver signal having a low voltage state and transmitting said second row driver signal through said row driver transistor for every other row line for holding said every other row line at ground.