US4145622A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Decoder circuit arrangement with MOS transistors
Assignee: Siemens AG
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Filing: 1977-08-17
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Granted: 1979-03-20
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Expires: 1997-08-17
Abstract
Abstract A decoder circuit arrangement with MOS transistors includes a decoder circuit and an output stage. The output stage includes a driver transistor which emits a selection signal, in accordance with a decoder signal emitted from the decoder circuit, and includes a shunt transistor having a controlled path connected between the output of the decoder circuit and the output of the output stage and a control input which is supplied with the selection signal. An additional transistor has a controlled path connected between the output of the output stage and a fixed potential and a control input which is driven by a timing signal which renders the additional transistor conductive, at least during the time in which the selection signal is not present.
Inventors
- 👤 Ruediger Hofmann
- 👤 Paul-Werner von Basse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:53
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4087; G11C11/4085; H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01742; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
200 words
A decoder circuit arrangement comprising a decoder circuit comprising a plurality of parallel-connected MOS transistors having a plurality of inputs for receiving signals to be decoded and a decoder output for emitting a decoded signal, an output stage including an input connected to said output of said decoder circuit and having an output, and a pair of control signal inputs, an MOS driver transistor in said output stage including a controlled path connected between one of said control inputs for receiving a selection signal, and said output of said output stage and including a gate connected to said output of said decoder circuit, a shunt MOS transistor in said output stage including a controlled path connected between said output of said decoder circuit and said output of said output stage and having a gate connected to said one control input, and an additional MOS transistor in said output stage including a controlled path connected between said output of said output stage and a fixed potential and a gate connected to the other of said control inputs for receiving a timing signal which renders said additional transistor conductive at least during the time in which the selection signal is not present.
Claim 2
Dependent Claim
200 words
A decoder circuit arrangement comprising a decoder circuit comprising a plurality of parallel-connected MOS transistors having a plurality of inputs for receiving signals to be decoded and a decoder output for emitting a decoded signal, an output stage including an input connected to said output of said decoder circuit and having an output, and a pair of control signal inputs, an MOS driver transistor in said output stage including a controlled path connected between one of said control inputs for receiving a selection signal, and said output of said output stage and including a gate connected to said output of said decoder circuit, a shunt MOS transistor in said output stage including a controlled path connected between said output of said decoder circuit and said output of said output stage and having a gate connected to said one control input, and an additional MOS transistor in said output stage including a controlled path connected between said output of said output stage and a fixed potential and a gate connected to the other of said control inputs for receiving a timing signal which renders said additional transistor conductive at least during the time in which the selection signal is not present.
Claim 3
Dependent Claim
34 words
The decoder circuit arrangement of claim 1, comprising: means for rendering said timing signal effective to render said additional MOS transistor conductive prior to the occurrence of the trailing edge of said selection signal.
Claim 4
Dependent Claim
32 words
The decoder circuit arrangement of claim 1, comprising: means for discharging the output of said decoder circuit including said shunt MOS transistor connected between said decoder circuit and said additional MOS transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-19 | 1982-09-18 | 1983-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-19 | 1986-09-18 | 1987-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-19 | 1990-09-18 | 1991-03-20 | $7700.00 | Window Closed / Lapsed |