US5079446A
Expired / Lapsed
US
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Circuit configuration for generating combinatorial binary logic functions with multiplexers and inverters
Assignee: Siemens AG
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Filing: 1990-09-21
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Granted: 1992-01-07
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Expires: 2010-09-21
Abstract
Abstract A circuit configuration for generating combinatorial logic functions includes a plurality of cascading circuit blocks, which are each formed of a 1-out-of-4 multiplexer and an inverter. Control inputs of the multiplexer are acted upon by input variables having a higher significance and data inputs are acted upon by a logical zero, a logical one, least significant input variables or inverted least significant input variables, in dependence on a linking function.
Inventors
- 👤 Josef Holzle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
219 words
Circuit configuration for generating a binary logic function, comprising: a) means for generating more than one output signal from three input signals in accordance with the logic function; b) a plurality of circuit blocks each having three inputs and an output for producing one output signal from the three input signals according to logic sub-functions comprising the logic function; c) said circuit blocks each including an inverter and a 1-out-of-4 multiplexer having two control inputs, four data inputs and one data output; d) said two control inputs of each of said 1-out-of-4 multiplexers being connected to two of said three inputs of a respective one of said circuit blocks; e) said data output of each of said 1-out-of-4 multiplexers being connected with said output of a respective one of said circuit blocks; f) each of said data inputs of each of said 1-out-of-4 multiplexers, depending on said logic sub-function to be realized, being connected with one of the third of said three inputs of a respective one of said circuit blocks, the third input of said three inputs of a respective one of said circuit blocks inverted by said inverter, a potential corresponding to a logical 1, and a potential corresponding to a logical 0; and g) said inputs of said plurality of circuit blocks being connected in parallel.
Claim 2
Dependent Claim
219 words
Circuit configuration for generating a binary logic function, comprising: a) means for generating more than one output signal from three input signals in accordance with the logic function; b) a plurality of circuit blocks each having three inputs and an output for producing one output signal from the three input signals according to logic sub-functions comprising the logic function; c) said circuit blocks each including an inverter and a 1-out-of-4 multiplexer having two control inputs, four data inputs and one data output; d) said two control inputs of each of said 1-out-of-4 multiplexers being connected to two of said three inputs of a respective one of said circuit blocks; e) said data output of each of said 1-out-of-4 multiplexers being connected with said output of a respective one of said circuit blocks; f) each of said data inputs of each of said 1-out-of-4 multiplexers, depending on said logic sub-function to be realized, being connected with one of the third of said three inputs of a respective one of said circuit blocks, the third input of said three inputs of a respective one of said circuit blocks inverted by said inverter, a potential corresponding to a logical 1, and a potential corresponding to a logical 0; and g) said inputs of said plurality of circuit blocks being connected in parallel.
Claim 3
Dependent Claim
263 words
Circuit configuration for generating a binary logic function, comprising: a) means for generating a single output signal from more than three input signals in accordance with a logic function; b) a plurality of circuit blocks subdivided into first and second groups, each of said blocks having three inputs and an output for producing an output signal from the three input signals according to logic sub-functions comprising the logic functions; c) said circuit blocks each including an inverter and a 1-out-of-4 multiplexer having two control inputs, four data inputs and one data output; d) said two control inputs of each of said 1-out-of-4 multiplexers being connected to two of said three inputs of a respective one of said circuit blocks; e) said data output of each of said 1-out-of-4 multiplexers being connected with said output of a respective one of said circuit blocks; f) each of said data inputs of each of said 1-out-of-4 multiplexers, depending on said logic sub-function to be realized, being connected with one of the third of said three inputs of a respective one of said circuit blocks, the third input of said three inputs of a respective one of said circuit blocks inverted by said inverter, a potential corresponding to a logical 1, and a potential corresponding to a logical 0; g) said inputs of said circuit blocks of said first group each receiving three input signals of the circuit configuration, and said inputs of said circuit blocks of said second group each receiving the output signals of said first group and extraneous input signals of the circuit configuration.
Claim 4
Dependent Claim
263 words
Circuit configuration for generating a binary logic function, comprising: a) means for generating a single output signal from more than three input signals in accordance with a logic function; b) a plurality of circuit blocks subdivided into first and second groups, each of said blocks having three inputs and an output for producing an output signal from the three input signals according to logic sub-functions comprising the logic functions; c) said circuit blocks each including an inverter and a 1-out-of-4 multiplexer having two control inputs, four data inputs and one data output; d) said two control inputs of each of said 1-out-of-4 multiplexers being connected to two of said three inputs of a respective one of said circuit blocks; e) said data output of each of said 1-out-of-4 multiplexers being connected with said output of a respective one of said circuit blocks; f) each of said data inputs of each of said 1-out-of-4 multiplexers, depending on said logic sub-function to be realized, being connected with one of the third of said three inputs of a respective one of said circuit blocks, the third input of said three inputs of a respective one of said circuit blocks inverted by said inverter, a potential corresponding to a logical 1, and a potential corresponding to a logical 0; g) said inputs of said circuit blocks of said first group each receiving three input signals of the circuit configuration, and said inputs of said circuit blocks of said second group each receiving the output signals of said first group and extraneous input signals of the circuit configuration.
Claim 5
Dependent Claim
279 words
Circuit configuration for generating binary logic functions, comprising: a) means for generating more than one output signal from more than three input signals in accordance with a logic function; b) a plurality of first and second groups of circuit blocks connected in parallel on an input side, said groups each including a plurality of circuit blocks, each of said blocks having three inputs and an output for producing an output signal from the three input signals according to logic sub-functions comprising the logic function; c) said circuit blocks each including an inverter and a 1-out-of-4 multiplexer having two control inputs, four data inputs and one data output; d) said two control inputs of each of said 1-out-of-4 multiplexers being connected to two of said three inputs of a respective one of said circuit blocks; e) said data output of each of said 1-out-of-4 multiplexers being connected with said output of a respective one of said circuit blocks; f) each of said data inputs of each of said 1-out-of-4 multiplexers, depending on said logic sub-function to be realized, being connected with one of the third of said three inputs of a respective one of said circuit blocks, the third input of said three inputs of a respective one of said circuit blocks inverted by said inverter, a potential corresponding to a logical 1, and a potential corresponding to a logical 0; and g) said inputs of said circuit blocks of said first group each receiving three input signals of the circuit configuration, and said inputs of said circuit blocks of said second group each receiving the output signals of said first group and extraneous input signals of the circuit configuration.
Claim 6
Dependent Claim
279 words
Circuit configuration for generating binary logic functions, comprising: a) means for generating more than one output signal from more than three input signals in accordance with a logic function; b) a plurality of first and second groups of circuit blocks connected in parallel on an input side, said groups each including a plurality of circuit blocks, each of said blocks having three inputs and an output for producing an output signal from the three input signals according to logic sub-functions comprising the logic function; c) said circuit blocks each including an inverter and a 1-out-of-4 multiplexer having two control inputs, four data inputs and one data output; d) said two control inputs of each of said 1-out-of-4 multiplexers being connected to two of said three inputs of a respective one of said circuit blocks; e) said data output of each of said 1-out-of-4 multiplexers being connected with said output of a respective one of said circuit blocks; f) each of said data inputs of each of said 1-out-of-4 multiplexers, depending on said logic sub-function to be realized, being connected with one of the third of said three inputs of a respective one of said circuit blocks, the third input of said three inputs of a respective one of said circuit blocks inverted by said inverter, a potential corresponding to a logical 1, and a potential corresponding to a logical 0; and g) said inputs of said circuit blocks of said first group each receiving three input signals of the circuit configuration, and said inputs of said circuit blocks of said second group each receiving the output signals of said first group and extraneous input signals of the circuit configuration.
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| 3.5 Years (Year 4) | 1995-01-06 | 1995-07-08 | 1996-01-07 | $2000.00 | Window Closed / Lapsed |
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