US5541537A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed static circuit design
Assignee: International Business Machines Corp
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Filing: 1995-06-02
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Granted: 1996-07-30
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Expires: 2015-06-02
Abstract
Abstract Logic circuitry utilizing the advantages of static and dynamic design techniques utilize feed-forward from the inputs to the logic circuit and feed-back from the output of the logic circuit in order to provide a RESET signal to precharge the logic circuit to a predetermined state. This technique also provides for initialization of the circuit before the arrival of data input signals.
Inventors
- 👤 Song C. Kim
- 👤 Kuan-Yu J. Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
233 words
A logic circuit comprising: an input means for receiving two or more digital data signals; first and second N-FETs having their gate electrodes connected to said input means, wherein said first and second N-FETs are connected in series between a node and a first voltage source; a first P-FET connected between a second voltage source and said node; a second P-FET having its gate electrode coupled to said node, wherein said second P-FET is connected between said second voltage source and an output terminal; a third N-FET having its gate electrode coupled to said node and being connected between said first voltage source and said output terminal; a third P-FET connected between said second voltage source and said node and having its gate electrode coupled to said output terminal; a fourth N-FET connected between said first voltage source and said output terminal; a first NAND circuit having its inputs connected to said input means; a second NAND circuit having one of its inputs connected to an output of said first NAND circuit and having a second input coupled to said output terminal, wherein an output of said second NAND circuit is connected to a gate electrode of said first P-FET; and an inverter circuit having an input connected to said output of said second NAND circuit, wherein an output of said inverter circuit is connected to a gate electrode of said fourth N-FET.
Claim 2
Dependent Claim
233 words
A logic circuit comprising: an input means for receiving two or more digital data signals; first and second N-FETs having their gate electrodes connected to said input means, wherein said first and second N-FETs are connected in series between a node and a first voltage source; a first P-FET connected between a second voltage source and said node; a second P-FET having its gate electrode coupled to said node, wherein said second P-FET is connected between said second voltage source and an output terminal; a third N-FET having its gate electrode coupled to said node and being connected between said first voltage source and said output terminal; a third P-FET connected between said second voltage source and said node and having its gate electrode coupled to said output terminal; a fourth N-FET connected between said first voltage source and said output terminal; a first NAND circuit having its inputs connected to said input means; a second NAND circuit having one of its inputs connected to an output of said first NAND circuit and having a second input coupled to said output terminal, wherein an output of said second NAND circuit is connected to a gate electrode of said first P-FET; and an inverter circuit having an input connected to said output of said second NAND circuit, wherein an output of said inverter circuit is connected to a gate electrode of said fourth N-FET.
Claim 3
Dependent Claim
239 words
A logic circuit comprising: two or more input terminals for receiving two or more digital data signals; first and second N-FETs coupled in parallel between a node and a first voltage source, wherein gate electrodes of said first and second N-FETs are connected to said two or more input terminals; a first P-FET connected between a second voltage source and said node; an output terminal; a second P-FET connected between said second voltage source and said output terminal, wherein a gate electrode of said second P-FET is connected to said node; a third P-FET connected between said second voltage source and said node, wherein a gate electrode of said third P-FET is connected to said output terminal; a third N-FET connected between said output terminal and said first voltage source, wherein a gate electrode of said third N-FET is connected to said node; a fourth N-FET connected between said output terminal and said first voltage source; a NOR circuit having its inputs connected to said two or more input terminals; a NAND circuit having a first input coupled to said output terminal and a second input connected to an output of said NOR circuit, wherein an output of said NAND circuit is connected to a gate electrode of said first P-FET; and an inverter circuit having its input connected to an output of said NAND circuit and having its output connected to a gate electrode of said fourth N-FET.
Claim 4
Dependent Claim
239 words
A logic circuit comprising: two or more input terminals for receiving two or more digital data signals; first and second N-FETs coupled in parallel between a node and a first voltage source, wherein gate electrodes of said first and second N-FETs are connected to said two or more input terminals; a first P-FET connected between a second voltage source and said node; an output terminal; a second P-FET connected between said second voltage source and said output terminal, wherein a gate electrode of said second P-FET is connected to said node; a third P-FET connected between said second voltage source and said node, wherein a gate electrode of said third P-FET is connected to said output terminal; a third N-FET connected between said output terminal and said first voltage source, wherein a gate electrode of said third N-FET is connected to said node; a fourth N-FET connected between said output terminal and said first voltage source; a NOR circuit having its inputs connected to said two or more input terminals; a NAND circuit having a first input coupled to said output terminal and a second input connected to an output of said NOR circuit, wherein an output of said NAND circuit is connected to a gate electrode of said first P-FET; and an inverter circuit having its input connected to an output of said NAND circuit and having its output connected to a gate electrode of said fourth N-FET.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-30 | 2000-01-29 | 2000-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-30 | 2004-01-29 | 2004-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-30 | 2008-01-29 | 2008-07-30 | $7700.00 | Window Closed / Lapsed |