Using cascode transistors having low threshold voltages

Claim 2

A logic circuit, comprising: a signal path; a high threshold voltage transistor having a first threshold voltage and coupled to said signal path; a source of a precharge voltage; a source of a clock signal having a precharge phase and an evaluate phase; a precharge node; a precharge device connected to the source of the precharge voltage, the source of the clock signal and the precharge node, the precharge device operable to connect the precharge node to the precharge voltage during the precharge phase of the clock signal, thereby precharging the precharge node to the precharge voltage; and a conditional series discharge path connected to said precharge node, receiving first and second logic input signals and operable to couple said precharge node to a voltage different than the precharge voltage dependent upon a logic state of the respective first and second logic input signals, wherein said conditional series discharge path comprises: a first low threshold voltage transistor having a second threshold voltage lower in magnitude than the first threshold voltage, a gate receiving the first logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the first logic input signal, wherein the first logic input signal is disabling during the precharge phase such that said conductive path of said first low threshold voltage transistor is not conducting during the precharge phase; and a second low threshold voltage transistor having the second threshold voltage, a gate receiving the second logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the second logic input signal, wherein the second logic input signal is disabling during the precharge phase such that said conductive path of said second low threshold voltage transistor is not conducting during the precharge phase.

Claim 3

The logic circuit of claim 1 wherein said conditional series discharge path further comprises one or more additional low threshold voltage transistors, wherein each of said one or more additional low threshold voltage transistors has the second threshold voltage, a gate receiving a corresponding additional logic input signal and provides a conductive path along said conditional series discharge path.

Claim 4

The logic circuit of claim 1 wherein said conditional series discharge path further comprises one or more additional low threshold voltage transistors and provides a conductive path along said conditional series discharge path, wherein each of said one or more additional low threshold voltage transistors has the second threshold voltage and wherein each of said one or more additional low threshold voltage transistors has a gate receiving a corresponding additional logic input signal which is disabling during the precharge phase such that said conductive path of each of said one or more additional low threshold voltage transistors is not conducting during the precharge phase.

Claim 5

The logic circuit of claim 1 wherein said conductive path provided by said first low threshold voltage transistor is directly connected to said conductive path provided by said second low threshold voltage transistor.

Claim 6

The logic circuit of claim 1 wherein said conductive path provided by said first low threshold voltage transistor is not directly connected to said conductive path provided by said second low threshold voltage transistor.

Claim 7

The logic circuit of claim 1: wherein the first logic input signal is provided by an output of a dynamic logic circuit such that said first low threshold voltage transistor is disabled during the precharge phase such that said conductive path of said first low threshold voltage transistor is not conducting during the precharge phase; and wherein the second logic input signal is provided by an output of a dynamic logic circuit such that said second low threshold voltage transistor is disabled during the precharge phase such that said conductive path of said second low threshold voltage transistor is not conducting during the precharge phase.

Claim 8

The logic circuit of claim 1 wherein each of said first and second low threshold voltage transistors comprises an n-channel transistor.

Claim 9

The logic circuit of claim 1 wherein each of said first and second low threshold voltage transistors comprises a p-channel transistor.

Claim 10

The logic circuit of claim 1 wherein said precharge device comprises a p-channel transistor having a source connected to the source of the precharge voltage, a drain connected to said precharge node, and a gate receiving the clock signal.

Claim 11

The logic circuit of claim 1 wherein said first low threshold voltage transistor is formed using a first implantation step and wherein said high threshold voltage transistor is formed using a second implantation step at a time different than said first implantation step.

Claim 12

The logic circuit of claim 1 wherein said conditional series discharge path further comprises a third low threshold voltage transistor having the second threshold voltage, a gate receiving a third logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon a logic state of the third logic input signal.

Claim 13

The logic circuit of claim 11 wherein the third logic input signal is disabling during the precharge phase such that said conductive path of said third low voltage transistor is not conducting during the precharge phase.

Claim 14

The logic circuit of claim 1: wherein said conditional series discharge path comprises a first conditional series discharge path; and further comprising a second conditional series discharge path connected to said precharge node, receiving at least one additional logic input signal and operable to conditionally couple said precharge node to the voltage different than the precharge voltage dependent upon a logic state of the at least one additional logic input signal.

Claim 15

The logic circuit of claim 13 wherein said second conditional series discharge path comprises: a third low threshold voltage transistor having the second threshold voltage, a gate receiving a third logic input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon a logic state of the third logic input signal, wherein the third logic input signal is disabling during the precharge phase such that said conductive path of said third low threshold voltage transistor is not conducting during the precharge phase; and a fourth low threshold voltage transistor having the second threshold voltage, a gate receiving a fourth logic input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon a logic state of the fourth logic input signal, wherein the fourth logic input signal is disabling during the precharge phase such that said conductive path of said fourth low threshold voltage transistor is not conducting during the precharge phase.

Claim 16

The logic circuit of claim 1 wherein the first logic input signal is provided by a gated clock signal having a logic state during the precharge phase such that said first low threshold voltage transistor is disabled during the precharge phase such that said conductive path of said first low threshold voltage transistor is not conducting during the precharge phase and having an optional logic state during said evaluate phase such that said first low threshold transistor is optionally enabled during the evaluate phase such that said conductive path of the first low threshold voltage transistor is conditionally conducting during the evaluate phase depending upon the logic state of the first logic input signal.

Claim 17

The logic circuit of claim 15 wherein the second logic input signal is provided by an output of a dynamic logic circuit having a logic state during the precharge phase such that said second low threshold voltage transistor is disabled during the precharge phase such that said conductive path of said second low threshold voltage transistor is not conducting during the precharge phase and having an optional logic state during said evaluate phase such that said second low threshold transistor is optionally enabled during the evaluate phase such that said conductive path of said second low threshold voltage transistor is conditionally conducting during the evaluate phase depending upon the logic state of the second logic input signal.

Claim 18

The logic circuit of claim 1 and further comprising an inverter having an input coupled to said precharge node.

Claim 19

The logic circuit of claim 17 and further comprising a p-channel transistor a having a source connected to the source of the precharge voltage, a drain connected to said precharge node, and a gate connected to an output of said inverter.

Claim 20

The logic circuit of claim 1 wherein said high threshold voltage transistor comprises a first high threshold voltage transistor, and wherein said conditional series discharge path further comprises a second high threshold voltage transistor having the first threshold voltage, a gate receiving a third logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon a logic state of the third logic input signal.

Claim 21

The logic circuit of claim 19 wherein the third logic input signal is operable to be disabling during the precharge phase of operation such that said conductive path of said second high threshold voltage transistor is not conducting during the precharge phase.

Claim 22

The logic circuit of claim 20: wherein said conductive path provided by said first low threshold voltage transistor is directly connected to said conductive path provided by said second low threshold voltage transistor; and wherein said conductive path provided by said second high threshold voltage transistor is directly connected to said conductive path provided by said first low threshold voltage transistor.

Claim 23

The logic circuit of claim 20: wherein said conductive path provided by said first low threshold voltage transistor is directly connected to said conductive path provided by said second high threshold voltage transistor; and wherein said conductive path provided by said second high threshold voltage transistor is directly connected to said conductive path provided by said second low threshold voltage transistor.

Claim 24

The logic circuit of claim 1 wherein each of said first low threshold voltage transistor and said high threshold voltage transistor comprises a silicon-on-insulator transistor.

Claim 25

The logic circuit of claim 23 wherein said first low threshold voltage transistor comprises a body connection, and wherein said body connection floats.

Claim 26

The logic circuit of claim 23 wherein said high threshold voltage transistor comprises a body connection and a gate, and wherein said body connection is connected to said gate.

Claim 27

The logic circuit of claim 23 wherein said high threshold voltage transistor is an n-channel transistor comprising a body connection and a source, and wherein said body connection is connected to said source.

Claim 28

The logic circuit of claim 23 wherein said high threshold voltage transistor is an n-channel transistor comprising a body connection, and wherein said body connection is connected to ground.

Claim 29

The logic circuit of claim 23 wherein said high threshold voltage transistor is an n-channel transistor comprising a body connection, and wherein said body connection is connected to said precharge voltage.

Claim 30

A logic circuit comprising: a first signal path; a first high threshold voltage transistor having a first threshold voltage and coupled to said first signal path; a source of a first precharge voltage; a source of a clock signal having a precharge phase and an evaluate phase; a first precharge node; a first precharge device connected to the source of the first precharge voltage, the source of the clock signal and the first precharge node, the first precharge device operable to connect the first precharge node to the first precharge voltage during the precharge phase of the clock signal, thereby precharging the first precharge node to the first precharge voltage; and a first conditional series discharge path connected to said first precharge node, receiving first and second logic input signals and operable to conditionally couple said first precharge node to a voltage different than the first precharge voltage dependent upon a logic state of the respective first and second logic input signals, wherein said first conditional series discharge path comprises: a first low threshold voltage transistor having a second threshold voltage lower in magnitude than the first threshold voltage, a gate receiving the first logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the first logic input signal, wherein the first logic input signal is disabling during the precharge phase such that said conductive path of said first low threshold voltage transistor is not conducting during the precharge phase; a second low threshold voltage transistor having the second threshold voltage, a gate receiving the second logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the second logic input signal, wherein the second logic input signal is disabling during the precharge phase such that said conductive path of said second low threshold voltage transistor is not conducting during the precharge phase; a second signal path; a source of a second precharge voltage; a second high threshold voltage transistor of a second conductivity type and having a first threshold voltage corresponding to the second conductivity type coupled to the second signal path; a second precharge node; a second precharge device connected to the source of the clock signal, the source of the second precharge voltage and the second precharge node and operative to connect the second precharge node to the second precharge voltage during the precharge phase of the clock signal, thereby precharging the second precharge node to second the precharge voltage; and a second conditional series discharge path connected to said second precharge node, receiving third and fourth logic input signals and operable to conditionally couple said second precharge node to a voltage different than the second precharge voltage dependent upon a logic state of the third and fourth logic input signals, wherein said second conditional series discharge path connected to said second precharge node comprises: a first low threshold voltage transistor of the second conductivity type and having a second threshold voltage corresponding to the second conductivity type and lower in magnitude than the first threshold voltage corresponding to the second conductivity type, a gate receiving the third logic input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon the logic state of the third input signal, wherein the third logic input signal is disabling during the precharge phase such that said conductive path of said first low threshold voltage transistor is not conducting during the precharge phase; and a second low threshold voltage transistor of the second conductivity type and having the second threshold voltage corresponding to the second conductivity type, a gate receiving the fourth logic input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon the logic state of the fourth logic input signal, wherein the fourth logic input signal is disabling during the precharge phase such that said conductive path of said second low threshold voltage transistor is not conducting during the precharge phase; wherein the voltage at the first precharge node provides one of said third or fourth input signals.

Claim 31

A logic circuit comprising: a first signal path; a first high threshold voltage transistor having a first threshold voltage and coupled to said first signal path; a source of a first precharge voltage; a source of a clock signal having a precharge phase and an evaluate phase; a first precharge node; a first precharge device connected to the source of the first precharge voltage, the source of the clock signal and the first precharge node, the first precharge device operable to connect the first precharge node to the first precharge voltage during the precharge phase of the clock signal, thereby precharging the first precharge node to the first precharge voltage; and a first conditional series discharge path connected to said first precharge node, receiving first and second logic input signals and operable to conditionally couple said first precharge node to a voltage different than the first precharge voltage dependent upon a logic state of the respective first and second logic input signals, wherein said first conditional series discharge path comprises: a first low threshold voltage transistor having a second threshold voltage lower in magnitude than the first threshold voltage, a gate receiving the first logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the first logic input signal, wherein the first logic input signal is disabling during the precharge phase such that said conductive path of said first low threshold voltage transistor is not conducting during the precharge phase; a second low threshold voltage transistor having the second threshold voltage, a gate receiving the second logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the second logic input signal, wherein the second logic input signal is disabling during the precharge phase such that said conductive path of said second low threshold voltage transistor is not conducting during the precharge phase; a second signal path; a source of a second precharge voltage; a second high threshold voltage transistor of a second conductivity type and having a first threshold voltage corresponding to the second conductivity type coupled to the second signal path; a second precharge node; a second precharge device connected to the source of the clock signal, the source of the second precharge voltage and the second precharge node and operative to connect the second precharge node to the second precharge voltage during the precharge phase of the clock signal, thereby precharging the second precharge node to second the precharge voltage; and a second conditional series discharge path connected to said second precharge node, receiving third and fourth logic input signals and operable to conditionally couple said second precharge node to a voltage different than the second precharge voltage dependent upon a logic state of the third and fourth logic input signals, wherein said second conditional series discharge path connected to said second precharge node comprises: a first low threshold voltage transistor of the second conductivity type and having a second threshold voltage corresponding to the second conductivity type and lower in magnitude than the first threshold voltage corresponding to the second conductivity type, a gate receiving the third logic input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon the logic state of the third input signal, wherein the third logic input signal is disabling during the precharge phase such that said conductive path of said first low threshold voltage transistor is not conducting during the precharge phase; and a second low threshold voltage transistor of the second conductivity type and having the second threshold voltage corresponding to the second conductivity type, a gate receiving the fourth logic input signal and conditionally providing a conductive path along said second conditional series discharge path dependent upon the logic state of the fourth logic input signal, wherein the fourth logic input signal is disabling during the precharge phase such that said conductive path of said second low threshold voltage transistor is not conducting during the precharge phase; wherein the voltage at the first precharge node provides one of said third or fourth input signals.

Claim 32

A logic circuit comprising: a signal path; a high threshold voltage transistor having a first threshold voltage and coupled to said signal path; a source of a precharge voltage; a source of a clock signal having a precharge phase and an evaluate phase; a precharge node; a precharge device connected to the source of the precharge voltage, the source of the clock signal and the precharge node, the precharge device operable to connect the precharge node to the precharge voltage during the precharge phase of the clock signal, thereby precharging the precharge node to the precharge voltage; and a conditional series discharge path connected to said precharge node, receiving first and second logic input signals and operable to couple said precharge node to a voltage different than the precharge voltage dependent upon a logic state of the respective first and second logic input signals, wherein said conditional series discharge path comprises: a first low threshold voltage transistor having a second threshold voltage lower in magnitude than the first threshold voltage, a gate receiving the first logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the first logic input signal, wherein the first logic input signal is disabling during the precharge phase such that said conductive path of said first low threshold voltage transistor is not conducting during the precharge phase; and a second low threshold voltage transistor having the second threshold voltage, a gate receiving the second logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the second logic input signal, wherein the second logic input signal is disabling during the precharge phase such that said conductive path of said second low threshold voltage transistor is not conducting during the precharge phase; wherein said precharge node and said conditional series discharge path are included in a first phase dynamic logic circuit comprising one or more dynamic logic stages; wherein each of said one or more dynamic logic stages of said first phase dynamic logic circuit comprises a precharge node and a conditional series discharge path; wherein each precharge node of each of said one or more dynamic logic stages is further coupled to a precharge device which when conducting couples said precharge node to a precharge voltage during said precharge phase; and further comprising a second phase dynamic logic circuit comprising one or more dynamic logic stages, wherein each of said one or more dynamic logic stages of second phase dynamic logic circuit comprises: a precharge node; a conditional series discharge path connected to said precharge node and operable to conditionally couple said precharge node to a voltage different than the precharge voltage; and a precharge device coupled to the source of the precharge voltage, the source of the clock signal and said precharge node of said second phase dynamic logic circuit operable to connect the precharge node to the precharge voltage during the precharge phase of the clock signal, thereby precharging the precharge node to the precharge voltage; wherein each of said dynamic logic stages further comprises an output for presenting a logic value responsive to a voltage at said precharge node; and further comprising control circuitry for controlling at least one of said dynamic logic stages as a storing stage such that said conditional series discharge path and said precharge device are not concurrently conducting during a predetermined time such that the logic value is maintained at said output, wherein the predetermined time is equal to or greater than a time period equal to said evaluate phase plus said precharge phase.

Claim 33

A logic circuit comprising: a signal path; a high threshold voltage transistor having a first threshold voltage and coupled to said signal path; a source of a precharge voltage; a source of a clock signal having a precharge phase and an evaluate phase; a precharge node; a precharge device connected to the source of the precharge voltage, the source of the clock signal and the precharge node, the precharge device operable to connect the precharge node to the precharge voltage during the precharge phase of the clock signal, thereby precharging the precharge node to the precharge voltage; and a conditional series discharge path connected to said precharge node, receiving first and second logic input signals and operable to couple said precharge node to a voltage different than the precharge voltage dependent upon a logic state of the respective first and second logic input signals, wherein said conditional series discharge path comprises: a first low threshold voltage transistor having a second threshold voltage lower in magnitude than the first threshold voltage, a gate receiving the first logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the first logic input signal, wherein the first logic input signal is disabling during the precharge phase such that said conductive path of said first low threshold voltage transistor is not conducting during the precharge phase; and a second low threshold voltage transistor having the second threshold voltage, a gate receiving the second logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the second logic input signal, wherein the second logic input signal is disabling during the precharge phase such that said conductive path of said second low threshold voltage transistor is not conducting during the precharge phase; wherein said precharge node and said conditional series discharge path are included in a first phase dynamic logic circuit comprising one or more dynamic logic stages; wherein each of said one or more dynamic logic stages of said first phase dynamic logic circuit comprises a precharge node and a conditional series discharge path; wherein each precharge node of each of said one or more dynamic logic stages is further coupled to a precharge device which when conducting couples said precharge node to a precharge voltage during said precharge phase; and further comprising a second phase dynamic logic circuit comprising one or more dynamic logic stages, wherein each of said one or more dynamic logic stages of second phase dynamic logic circuit comprises: a precharge node; a conditional series discharge path connected to said precharge node and operable to conditionally couple said precharge node to a voltage different than the precharge voltage; and a precharge device coupled to the source of the precharge voltage, the source of the clock signal and said precharge node of said second phase dynamic logic circuit operable to connect the precharge node to the precharge voltage during the precharge phase of the clock signal, thereby precharging the precharge node to the precharge voltage; wherein each of said dynamic logic stages further comprises an output for presenting a logic value responsive to a voltage at said precharge node; and further comprising control circuitry for controlling at least one of said dynamic logic stages as a storing stage such that said conditional series discharge path and said precharge device are not concurrently conducting during a predetermined time such that the logic value is maintained at said output, wherein the predetermined time is equal to or greater than a time period equal to said evaluate phase plus said precharge phase.

Claim 34

A logic circuit, comprising: a signal path; a high threshold voltage transistor having a first threshold voltage and coupled to said signal path; a source of a precharge voltage; a source of a clock signal having a precharge phase and an evaluate phase; a precharge node; a precharge device connected to the source of the precharge voltage, the source of the clock signal and the precharge node, the precharge device operable to connect the precharge node to the precharge voltage during the precharge phase of the clock signal, thereby precharging the precharge node to the precharge voltage; and a logic block connected to said precharge node, receiving at least two logic input signals and operable to couple said precharge node to a voltage different than the precharge voltage dependent upon a logic state of the respective logic input signals, said logic block consisting of at least one conditional series discharge path, each conditional series discharge path comprising at least one of the following: first and second low threshold voltage transistors, each having a second threshold voltage lower in magnitude than the first threshold voltage and a gate receiving the respective first and second logic input signals, the first and second low threshold voltage transistors having serially connected conductive paths conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the respective first and second logic input signals, wherein the first logic input signal is disabling the first low threshold voltage transistor and the second logic input signal is disabling the second logic input signal during the precharge phase such that said conductive paths of said first and second low threshold voltage transistors are not conducting during the precharge phase, or a second high threshold voltage transistor having the first threshold voltage, a gate receiving a third logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the third logic input signal, wherein the third logic input signal is disabling during the precharge phase such that said conductive path of said second high threshold voltage transistor is not conducting during the precharge phase.

Claim 35

A logic circuit, comprising: a signal path; a high threshold voltage transistor having a first threshold voltage and coupled to said signal path; a source of a precharge voltage; a source of a clock signal having a precharge phase and an evaluate phase; a precharge node; a precharge device connected to the source of the precharge voltage, the source of the clock signal and the precharge node, the precharge device operable to connect the precharge node to the precharge voltage during the precharge phase of the clock signal, thereby precharging the precharge node to the precharge voltage; and a logic block connected to said precharge node, receiving at least two logic input signals and operable to couple said precharge node to a voltage different than the precharge voltage dependent upon a logic state of the respective logic input signals, said logic block consisting of at least one conditional series discharge path, each conditional series discharge path comprising at least one of the following: first and second low threshold voltage transistors, each having a second threshold voltage lower in magnitude than the first threshold voltage and a gate receiving the respective first and second logic input signals, the first and second low threshold voltage transistors having serially connected conductive paths conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the respective first and second logic input signals, wherein the first logic input signal is disabling the first low threshold voltage transistor and the second logic input signal is disabling the second logic input signal during the precharge phase such that said conductive paths of said first and second low threshold voltage transistors are not conducting during the precharge phase, or a second high threshold voltage transistor having the first threshold voltage, a gate receiving a third logic input signal and conditionally providing a conductive path along said conditional series discharge path dependent upon the logic state of the third logic input signal, wherein the third logic input signal is disabling during the precharge phase such that said conductive path of said second high threshold voltage transistor is not conducting during the precharge phase.