US5821775A
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Method and apparatus to interface monotonic and non-monotonic domino logic
Assignee: Intel Corp
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Filing: 1996-12-27
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Granted: 1998-10-13
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Expires: 2016-12-27
Abstract
Abstract The present invention is an improved interface between monotonic and non-monotonic domino logic. A monotonic domino logic block is clocked by CLK. The last stage of the monotonic domino logic is clocked by the delayed clock, DCLK, to extend its evaluation period beyond Phase I by a brief window of time, t d . The true output and the inverted output of the last stage of the monotonic domino logic block are inputs to a non-monotonic domino evaluation tree. The non-monotonic domino evaluation tree operates while an evaluation control block is ON. The evaluation control block is ON only during that extension of the evaluation period, t d , for a time less than or equal to the period t d . Since the output of the last stage of the monotonic logic block remains stable during this extended evaluation period, and the non-monotonic domino evaluation tree operates at most during this window of time, there is no need to use latches or use a dual rail implementation for the monotonic logic.
Inventors
- 👤 Gaurav G. Mehta
- 👤 David Harris
- 👤 S. Deo Singh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
103 words
An interface between a monotonic domino logic block and a non-monotonic domino logic block comprising: a last stage of said monotonic domino logic block, said last stage being docked by a delayed clock; a evaluation control block; and the non-monotonic domino logic block having a first input which is an output of the last stage, and having a second input which is an inverted output of said last stage, said non-monotonic domino logic block operating during a window of time when said evaluation control block is ON, said window of time being less than or equal to a delay of said delayed clock.
Claim 2
Dependent Claim
103 words
An interface between a monotonic domino logic block and a non-monotonic domino logic block comprising: a last stage of said monotonic domino logic block, said last stage being docked by a delayed clock; a evaluation control block; and the non-monotonic domino logic block having a first input which is an output of the last stage, and having a second input which is an inverted output of said last stage, said non-monotonic domino logic block operating during a window of time when said evaluation control block is ON, said window of time being less than or equal to a delay of said delayed clock.
Claim 3
Dependent Claim
27 words
The interface of claim 1 wherein said window of time is longer than a period necessary to evaluate a function implemented by said non-monotonic domino logic block.
Claim 4
Dependent Claim
32 words
The interface of claim 1 wherein said evaluation control block comprises: a first n-type metal oxide semiconductor field effect device (NMOSFET); and a second NMOSFET connected to said first NMOSFET in series.
Claim 5
Dependent Claim
31 words
The interface of claim 1 wherein said evaluation control block comprises: an n-type metal oxide semiconductor field effect device (NMOSFET); and a pulse generator coupled to a gate of said NMOSFET.
Claim 6
Dependent Claim
20 words
The interface of claim 1 further comprising a keeper to keep an output of said non-monotonic domino logic block stable.
Claim 7
Dependent Claim
35 words
The interface of claim 5, wherein said keeper comprises: a first inverter; and a second inverter coupled in a series ring with said first inverter, connected to said output of said non-monotonic domino logic block.
Claim 8
Dependent Claim
29 words
The interface of claim 1 further comprising a second domino logic block, an input to said second domino logic block being said output of said non-monotonic domino logic block.
Claim 9
Dependent Claim
147 words
An interface between a monotonic domino logic block and a non-monotonic domino logic block comprising: a first clock signal; a complementary clock signal, said complementary clock signal being a complement of said first clock signal; a delayed clock signal, said delayed clock signal having a falling edge delayed with respect to said first clock signal; the monotonic domino logic block clocked by said first clock signal, having a last domino logic block clocked by said delayed clock signal; the non-monotonic domino logic block, having a first input which is an output of said last domino logic block, and having a second input which is an inverted output of said last domino logic block; and said non-monotonic domino logic block operating during a window of time comprising a time difference between a rising edge of said complementary clock signal and said falling edge of said delayed clock signal.
Claim 10
Dependent Claim
147 words
An interface between a monotonic domino logic block and a non-monotonic domino logic block comprising: a first clock signal; a complementary clock signal, said complementary clock signal being a complement of said first clock signal; a delayed clock signal, said delayed clock signal having a falling edge delayed with respect to said first clock signal; the monotonic domino logic block clocked by said first clock signal, having a last domino logic block clocked by said delayed clock signal; the non-monotonic domino logic block, having a first input which is an output of said last domino logic block, and having a second input which is an inverted output of said last domino logic block; and said non-monotonic domino logic block operating during a window of time comprising a time difference between a rising edge of said complementary clock signal and said falling edge of said delayed clock signal.
Claim 11
Dependent Claim
30 words
The interface of claim 8 wherein a delay of said delayed clock signal is greater than a period necessary to evaluate a function implemented by said non-monotonic domino logic block.
Claim 12
Dependent Claim
20 words
The interface of claim 8 wherein said window of time is less than a delay of said delayed clock signal.
Claim 13
Dependent Claim
60 words
The interface of claim 8 wherein said window of time is determined by a evaluation control block comprising: a first n-type metal oxide semiconductor field effect device (NMOSFET) having its gate coupled to said complementary clock signal; and a second NMOSFET having its gate connected to said delayed clock signal, said second NMOSFET connected in series to said first NMOSFET.
Claim 14
Dependent Claim
29 words
The interface of claim 8 further comprising a keeper for keeping said output of said non-monotonic domino logic block stable after said non-monotonic domino logic block ceases to operate.
Claim 15
Dependent Claim
35 words
The interface of claim 12, wherein said keeper comprises: a first inverter; and a second inverter connected with said first inverter in a series ring, connected to said output of said non-monotonic domino logic block.
Claim 16
Dependent Claim
29 words
The interface of claim 8 further comprising a second domino logic block, an input to said second domino logic block being said output of said non-monotonic domino logic block.
Claim 17
Independent Claim
122 words
A method of interfacing a monotonic domino logic block and a non-monotonic domino evaluation tree, said method comprising the steps of: generating a first output of a last block of a first monotonic domino logic block during an extended period, said extended period extending beyond a first clock phase by a delay of a delayed clock; turning on an evaluation control block for a window of time less than a second clock phase, which is less than or equal to the delay of the delayed clock; and generating a second output of the non-monotonic domino evaluation tree, said first output being an input to said non-monotonic domino evaluation tree, said non-monotonic domino evaluation tree operating while said evaluation control block is on.
Claim 18
Independent Claim
122 words
A method of interfacing a monotonic domino logic block and a non-monotonic domino evaluation tree, said method comprising the steps of: generating a first output of a last block of a first monotonic domino logic block during an extended period, said extended period extending beyond a first clock phase by a delay of a delayed clock; turning on an evaluation control block for a window of time less than a second clock phase, which is less than or equal to the delay of the delayed clock; and generating a second output of the non-monotonic domino evaluation tree, said first output being an input to said non-monotonic domino evaluation tree, said non-monotonic domino evaluation tree operating while said evaluation control block is on.
Claim 19
Dependent Claim
16 words
The method of claim 15 wherein said window of time starts during said second clock phase.
Claim 20
Dependent Claim
26 words
The method of claim 15 wherein said window of time is longer than a period for evaluating a function implemented in said non-monotonic domino evaluation tree.
Claim 21
Dependent Claim
16 words
The method of claim 15 wherein said window of time is shorter than said extended period.
Claim 22
Dependent Claim
23 words
The method of claim 15 further comprising the step of latching said second output by a keeper to keep said second output stable.
Claim 23
Dependent Claim
16 words
The method of claim 19 wherein said keeper comprises two inverters coupled in a series ring.
Claim 24
Dependent Claim
44 words
The method of claim 15 wherein said step of turning on said evaluation control block comprises: turning on a first n-type metal oxide semiconductor field effect device (NMOSFET); and turning on a second NMOSFET, said second NMOSFET coupled in series with said first NMOSFET.
Claim 25
Dependent Claim
49 words
The method of claim 15 wherein said step of turning on said evaluation control block comprises turning on an n-type metal oxide semiconductor field effect device (NMOSFET), by having its gate connected to a pulse generator, said pulse generator generating a pulse during which said NMOSFET is turned on.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |