Patent US4589707A successfully refreshed from Google Patents.
Patent US6048769A successfully refreshed from Google Patents.
US6048769A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers
Assignee: Intel Corp
•
Filing: 1998-03-30
•
Granted: 2000-04-11
•
Expires: 2018-03-30
Abstract
Abstract A CMOS integrated circuit having a PMOS and NMOS device with different gate dielectric layers. According to the present invention, an NMOS transistor is formed on a p-type conductivity region of a semiconductor substrate. The NMOS transistor has first gate dielectric layer formed on the p-type conductivity region. A PMOS transistor is formed on a n-type conductivity region of the semiconductor substrate. The PMOS transistor has a second gate dielectric layer wherein the second gate dielectric layer has a different composition than the first gate dielectric layer.
Inventors
- 👤 Robert S. Chau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:51
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0181; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/8314; H10D84/85; H10D84/856
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
105 words
A method of forming an integrated circuit on a semiconductor substrate comprising the steps of: forming a first dielectric layer on a first portion of said substrate; forming a second dielectric layer on a second portion of said substrate and on said first dielectric layer over said first portion of said substrate; forming a third dielectric layer over said second dielectric layer over said second portion of said substrate; forming a first gate electrode over said second dielectric layer over said first portion of said substrate; and forming a second gate electrode over said third dielectric layer over said second portion of said semiconductor substrate.
Claim 2
Independent Claim
105 words
A method of forming an integrated circuit on a semiconductor substrate comprising the steps of: forming a first dielectric layer on a first portion of said substrate; forming a second dielectric layer on a second portion of said substrate and on said first dielectric layer over said first portion of said substrate; forming a third dielectric layer over said second dielectric layer over said second portion of said substrate; forming a first gate electrode over said second dielectric layer over said first portion of said substrate; and forming a second gate electrode over said third dielectric layer over said second portion of said semiconductor substrate.
Claim 3
Dependent Claim
23 words
The method of claim 1 wherein said first substrate portion is n type conductivity and said second substrate portion is p type conductivity.
Claim 4
Dependent Claim
21 words
The method of claim 1 wherein said first dielectric layer is made of the same material as said third dielectric layer.
Claim 5
Dependent Claim
15 words
The method of claim 3 wherein said third and first dielectric layers are silicon dioxide.
Claim 6
Dependent Claim
16 words
The method of claim 1 wherein said second dielectric layer is a high dielectric constant material.
Claim 7
Dependent Claim
14 words
The method of claim 5 wherein said high dielectric constant material is silicon nitride.
Claim 8
Independent Claim
98 words
A method of forming a CMOS integrated circuit comprising the steps of: nitriding a first portion of a semiconductor substrate; growing an oxide layer over said nitrided first portion of said semiconductor substrate and over a second portion of said semiconductor substrate; nitridating said grown oxide layer over said first and said second portions of said semiconductor substrate; and forming a first gate electrode over said nitridated grown oxide layer over said first portion of said semiconductor substrate and a second gate electrode over said nitridated grown oxide layer over said second portion of said semiconductor substrate portion.
Claim 9
Independent Claim
98 words
A method of forming a CMOS integrated circuit comprising the steps of: nitriding a first portion of a semiconductor substrate; growing an oxide layer over said nitrided first portion of said semiconductor substrate and over a second portion of said semiconductor substrate; nitridating said grown oxide layer over said first and said second portions of said semiconductor substrate; and forming a first gate electrode over said nitridated grown oxide layer over said first portion of said semiconductor substrate and a second gate electrode over said nitridated grown oxide layer over said second portion of said semiconductor substrate portion.
Claim 10
Dependent Claim
57 words
The method of claim 7 wherein the step of nitriding said first portion of said semiconductor substrate comprises the steps of: forming a sacrificial oxide layer over said first portion of said semiconductor substrate; implanting nitrogen atoms through said sacrificial oxide layer and into said first portion of said semiconductor substrate; and removing said sacrificial oxide layer.
Claim 11
Dependent Claim
30 words
The method of claim 7 wherein said first portion of said semiconductor substrate is p type conductivity and wherein said second portion of said semiconductor substrate is n type conductivity.
Claim 12
Dependent Claim
18 words
The method of claim 7 wherein said step of nitridating said oxide layer comprises a plasma nitridation process.
Claim 13
Dependent Claim
22 words
The method of claim 7 wherein said step of nitridating said oxide layer comprises a rapid thermal anneal in an ammonia ambient.
References Cited (Backward Citations)
US4200474A
Cited
US4266985A
Cited
US4651406A
Cited
US4869781A
Cited
US5101248A
Cited
US5258645A
Cited
US5241208A
Cited
US5254489A
Cited
US5237188A
Cited
US5449637A
Cited
US5327002A
Cited
US5532181A
Cited
US5244843A
Cited
US5497021A
Cited
US5528068A
Cited
US5596218A
Cited
US5668028A
Cited
US5576226A
Cited
US5578848A
Cited
US5633202A
Cited
US5432114A
Cited
US5502009A
Cited
US5716863A
Cited
US5714788A
Cited
US5763922A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-11 | 2003-10-11 | 2004-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-11 | 2007-10-11 | 2008-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-11 | 2011-10-11 | 2012-04-11 | $7700.00 | Window Closed / Lapsed |