US5633202A
Expired / Lapsed
US
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High tensile nitride layer
Assignee: Intel Corp
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Filing: 1996-06-06
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Granted: 1997-05-27
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Expires: 2016-06-06
Abstract
Abstract An insulating layer in a semiconductor device and a process for forming the insulating layer is described. The insulating layer comprises of a nitride layer over the substrate having a residual stress of between -8×10 9 dynes/cm -2 and -3×10 10 dynes/cm -2 . The insulating layer can further comprise a doped oxide layer under the nitride layer and can further comprise an interlevel dielectric layer over the nitride layer. Moreover, the nitride layer can be formed by bringing the temperature in a chemical vapor deposition reactor to below 550 degrees Celsius, placing the substrate into the reactor at the temperature, and forming the nitride layer on the substrate. Alternatively, the nitride layer can be formed by pushing the substrate into a chemical vapor deposition reactor at a speed greater than 300 millimeters per minute, and forming the nitride layer on the substrate.
Inventors
- 👤 Lawrence N. Brigham
- 👤 Yung-Huei Lee
- 👤 Robert S. Chau
- 👤 Raymond E. Cotner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:52
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/0223; H10D30/0227; H10D30/60; H10D30/791; H10D30/792; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6923; H10P14/66; H10P14/668; H10P14/6681; H10P14/6682; H10P14/6684; H10P14/6686; Y; Y10; Y10S; Y10S438/00; Y10S438/954
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
62 words
A method of forming a semiconductor device, said method comprising the steps of: forming a transistor on said semiconductor substrate, said transistor having at least one silicide region; forming a doped oxide layer on said transistor including said silicide layer; forming a nitride layer having a tensile stress over said doped oxide layer; and forming an interlayer dielectric on said nitride layer.
Claim 2
Independent Claim
62 words
A method of forming a semiconductor device, said method comprising the steps of: forming a transistor on said semiconductor substrate, said transistor having at least one silicide region; forming a doped oxide layer on said transistor including said silicide layer; forming a nitride layer having a tensile stress over said doped oxide layer; and forming an interlayer dielectric on said nitride layer.
Claim 3
Dependent Claim
16 words
The method of claim 1 wherein said doped oxide layer is a phosphorous doped oxide layer.
Claim 4
Dependent Claim
16 words
The method of claim 1 wherein said doped oxide layer is a boron doped oxide layer.
Claim 5
Dependent Claim
17 words
The method of claim 1 wherein said nitride layer is formed by low pressure chemical vapor deposition.
Claim 6
Dependent Claim
24 words
The method of claim 4 wherein said nitride layer has a tensile stress between 8×10 9 dynes/cm 2 and 3×10 10 dynes/cm 2 .
Claim 7
Independent Claim
76 words
A method of forming a semiconductor device, said method comprising the steps of: forming a transistor having a source, gate, and drain; forming a refractory metal silicide on said source and said drain; forming a doped oxide layer over said transistor and on said refractory metal silicide on said source and said drain; forming a nitride layer having a residual tensile stress on said doped oxide layer; and forming an interlayer dielectric on said nitride layer.
Claim 8
Independent Claim
76 words
A method of forming a semiconductor device, said method comprising the steps of: forming a transistor having a source, gate, and drain; forming a refractory metal silicide on said source and said drain; forming a doped oxide layer over said transistor and on said refractory metal silicide on said source and said drain; forming a nitride layer having a residual tensile stress on said doped oxide layer; and forming an interlayer dielectric on said nitride layer.
Claim 9
Dependent Claim
23 words
The method of claim 6 wherein said transistor is a PMOS transistor and said doped oxide layer is a boron doped oxide layer.
Claim 10
Dependent Claim
23 words
The method of claim 6 wherein said transistor is a NMOS transistor and said doped oxide layer is a phosphorous doped oxide layer.
Claim 11
Dependent Claim
17 words
The method of claim 6 wherein said nitride layer is formed by low pressure chemical vapor deposition.
Claim 12
Dependent Claim
25 words
The method of claim 4 wherein said nitride layer has a tensile stress of between 8×10 9 dynes/cm 2 and 3×10 10 dynes/cm 2 .
Claim 13
Dependent Claim
23 words
The method of claim 9 wherein said substrate is pushed into a chemical vapor deposition reactor at a speed greater than 300 mm/minute.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-26 | 2000-11-25 | 2001-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-26 | 2004-11-25 | 2005-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-26 | 2008-11-25 | 2009-05-27 | $7700.00 | Window Closed / Lapsed |