Process of forming metal silicide interconnects

Claim 2

A process of forming an interconnect structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer; forming a layer of amorphous silicon over said layer of polysilicon; forming a layer of metal over said layer of amorphous silicon; and reacting said layer of amorphous silicon with said layer of metal to form a metal silicide structure.

Claim 3

The process of claim 1, wherein said layer of amorphous silicon has a thickness in the range of about 100 Angstroms to about 3,000 Angstroms.

Claim 4

The process of claim 2, wherein said layer of amorphous silicon has a thickness of approximately 1,000 Angstroms.

Claim 5

The process of claim 1, wherein said layer of metal comprises titanium.

Claim 6

The process of claim 1, wherein said layer of metal has a thickness in the range of about 30 Angstroms to about 2,000 Angstroms.

Claim 7

The process of claim 5, wherein said layer of metal has a thickness of approximately 500 Angstroms.

Claim 8

The process of claim 1, further comprising the step of patterning said layers of polysilicon, amorphous silicon and metal to form said interconnect structure.

Claim 9

The process of claim 7, wherein said step of patterning said layers of polysilicon, amorphous silicon and metal to form said interconnect structure is performed after said step of reacting said layer of amorphous silicon with said layer of metal to form a metal silicide structure.

Claim 10

The process of claim 1, wherein said step of forming a layer of amorphous silicon over said layer of polysilicon comprises the step of doping said layer of amorphous silicon with impurities.

Claim 11

The process of claim 9, wherein said impurities comprise phosphorous.

Claim 12

The process of claim 1, wherein said layer of amorphous silicon comprises amorphous silicon hydride.

Claim 13

A process of forming an interconnect structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer; forming a layer of amorphous silicon over said layer of polysilicon using plasma enhanced chemical vapor deposition (PECVD); forming a layer of metal over said layer of amorphous silicon; and reacting said layer of amorphous silicon with said layer of metal to form a metal silicide structure.

Claim 14

A process of forming an interconnect structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer; forming a layer of amorphous silicon over said layer of polysilicon using plasma enhanced chemical vapor deposition (PECVD); forming a layer of metal over said layer of amorphous silicon; and reacting said layer of amorphous silicon with said layer of metal to form a metal silicide structure.

Claim 15

The process of claim 12, wherein said step of forming a layer of amorphous silicon over said layer of polysilicon using PECVD comprises the step of forming Si and H free radicals by the decomposition of SiH 4 .

Claim 16

The process of claim 13, wherein said step of forming Si and H free radicals through the decomposition of SiH 4 comprises forming silicon hydride having a formula of SiH x , where x has a value from about 0.1 to about 5.

Claim 17

The process of claim 14, wherein PECVD is performed in a PECVD reactor, and said value of x is set by controlling at least one of the RF power, the temperature and pressure of said PECVD reactor.

Claim 18

The process of claim 14, wherein said step of forming a layer of amorphous silicon over said layer of polysilicon using PECVD comprises the step of dissolving H 2 in said layer of amorphous silicon.

Claim 19

The process of claim 16, wherein said step of dissolving H 2 in said layer of amorphous silicon is carried out through the decomposition of SiH 4 .

Claim 20

The process of claim 17, wherein an amount of dissolved H 2 is adjusted by controlling at least one of the RF power, temperature and pressure of a PECVD reactor.

Claim 21

The process of claim 16, wherein said step of reacting said layer of amorphous silicon with said layer of metal to form a metal silicide structure comprises the step of forming H radicals through the decomposition of said dissolved H 2 .

Claim 22

A process of forming an interconnect structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer; forming a layer of amorphous silicon over said layer of polysilicon; forming a layer of titanium over said layer of amorphous silicon; reacting said layer of amorphous silicon with said layer of titanium to form a C49 titanium silicide structure; and converting said C49 titanium silicide structure to a C54 titanium silicide structure.

Claim 23

A process of forming an interconnect structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer; forming a layer of amorphous silicon over said layer of polysilicon; forming a layer of titanium over said layer of amorphous silicon; reacting said layer of amorphous silicon with said layer of titanium to form a C49 titanium silicide structure; and converting said C49 titanium silicide structure to a C54 titanium silicide structure.

Claim 24

The process of claim 20, wherein said C54 titanium silicide structure has a sheet resistance less than 12 ohm/sq.

Claim 25

The process of claim 20, wherein said step of converting said C49 titanium silicide structure to a C54 titanium silicide structure comprises the step of annealing said C49 titanium silicide structure at a temperature ranging from about 700° C. to about 950° C. to convert it to said C54 titanium silicide structure.

Claim 26

A process of forming an interconnect structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer; forming a layer of amorphous silicon over said layer of polysilicon using plasma enhanced chemical vapor deposition (PECVD), said layer of amorphous silicon having a thickness in the range of about 100 Angstroms to about 3,000 Angstroms; forming a layer of titanium over said layer of amorphous silicon; and reacting said layer of amorphous silicon with said layer of titanium to form a titanium silicide structure.

Claim 27

A process of forming an interconnect structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer; forming a layer of amorphous silicon over said layer of polysilicon using plasma enhanced chemical vapor deposition (PECVD), said layer of amorphous silicon having a thickness in the range of about 100 Angstroms to about 3,000 Angstroms; forming a layer of titanium over said layer of amorphous silicon; and reacting said layer of amorphous silicon with said layer of titanium to form a titanium silicide structure.

Claim 28

The process of claim 23, wherein said step of reacting said layer of amorphous silicon with said layer of titanium to form a titanium silicide structure comprises the step of annealing said layer of amorphous silicon and said layer of titanium.

Claim 29

The process of claim 24, wherein said step of annealing said layer of amorphous silicon and said layer of titanium is carried out at a temperature ranging from about 500° C. to about 750° C.

Claim 30

A process of forming an interconnect structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer, said layer of polysilicon having a thickness in the range of about 500 Angstroms to about 1500 Angstroms; forming a layer of amorphous silicon over said layer of polysilicon using plasma enhanced chemical vapor deposition (PECVD) of SiH 4 , said layer of amorphous silicon having a thickness in the range of about 100 Angstroms to about 3,000 Angstroms and comprising free radicals having a formula of SiH x , where x has a value from about 0.1 to about 5; forming a layer of titanium over said layer of amorphous silicon using physical vapor deposition (PVD), said layer of titanium having a thickness in the range of about 30 Angstroms to about 2,000 Angstroms; reacting said layer of amorphous silicon with said layer of titanium at a temperature ranging from about 500° C. to about 750° C. to form a C49 titanium silicide structure; and annealing said C49 titanium silicide structure at a temperature ranging from about 700° C. to about 950° C. to convert it to a C54 titanium silicide structure.

Claim 31

A process of forming an interconnect structure comprising: providing at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer, said layer of polysilicon having a thickness in the range of about 500 Angstroms to about 1500 Angstroms; forming a layer of amorphous silicon over said layer of polysilicon using plasma enhanced chemical vapor deposition (PECVD) of SiH 4 , said layer of amorphous silicon having a thickness in the range of about 100 Angstroms to about 3,000 Angstroms and comprising free radicals having a formula of SiH x , where x has a value from about 0.1 to about 5; forming a layer of titanium over said layer of amorphous silicon using physical vapor deposition (PVD), said layer of titanium having a thickness in the range of about 30 Angstroms to about 2,000 Angstroms; reacting said layer of amorphous silicon with said layer of titanium at a temperature ranging from about 500° C. to about 750° C. to form a C49 titanium silicide structure; and annealing said C49 titanium silicide structure at a temperature ranging from about 700° C. to about 950° C. to convert it to a C54 titanium silicide structure.

Claim 32

A process of forming a field effect transistor having a self-aligned gate, said process comprising: providing a substrate assembly having at least one semiconductor layer; forming source and drain regions of said field effect transistor in said at least one semiconductor layer; forming a gate oxide for said self-aligned gate over said at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer and covering said gate oxide; forming a layer of amorphous silicon over said layer of polysilicon; forming a layer of titanium over said layer of amorphous silicon; and reacting said layer of amorphous silicon with said layer of metal to form a titanium silicide structure.

Claim 33

A process of forming a field effect transistor having a self-aligned gate, said process comprising: providing a substrate assembly having at least one semiconductor layer; forming source and drain regions of said field effect transistor in said at least one semiconductor layer; forming a gate oxide for said self-aligned gate over said at least one semiconductor layer; forming a layer of polysilicon over said at least one semiconductor layer and covering said gate oxide; forming a layer of amorphous silicon over said layer of polysilicon; forming a layer of titanium over said layer of amorphous silicon; and reacting said layer of amorphous silicon with said layer of metal to form a titanium silicide structure.

Claim 34

The process of claim 27, wherein a gate length of said gate is less than 0.1 μm.

Claim 35

The process of claim 27, further comprising the step of patterning said layers of polysilicon, amorphous silicon and titanium to form said, titanium silicide structure.