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US5904516A Expired / Lapsed US ⏱️ 0.0 years remaining

Transistor structure and method for fabricating the same

Assignee: SK Hynix Inc
•
Filing: 1997-04-09
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Granted: 1999-05-18
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Expires: 2017-04-09
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Abstract

Abstract A transistor including an insulating file, a gate, and a source/drain all formed on a semiconductor substrate, wherein the gate overlaps at an edge thereof with the source/drain disposed below the gate, whereby the transistor has a structure capable of avoiding a direct contact between the metal wiring and the source/drain. The gate is formed after a formation of the source/drain.

Inventors

  • 👤 Sang Hoon Park

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 23:07
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10P; H10P10/00; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0273; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 162 words
A method for fabricating a transistor including an insulating film, a gate, and a source/drain all formed on a semiconductor substrate, the gate overlapping at an edge thereof with the source/drain disposed below the gate, the method comprising: forming a field oxide film on the semiconductor substrate, sequentially forming an insulating film, a conduction film and another insulating film to predetermined thicknesses, and selectively etching the films such that the semiconductor substrate is exposed at a portion thereof disposed at a source/drain region; implanting impurity ions in the exposed portion of the semiconductor substrate, thereby forming the source/drain; forming a conduction film and an insulating film over the entire exposed surface obtained after the formation of the source/drain, and selectively etching the films, thereby forming a spacer disposed over the source/drain; and forming another insulating film and a polysilicon film over the entire exposed surface including said spacers and selectively etching the films, thereby forming a gate insulating film and the gate.
Claim 2
Independent Claim 162 words
A method for fabricating a transistor including an insulating film, a gate, and a source/drain all formed on a semiconductor substrate, the gate overlapping at an edge thereof with the source/drain disposed below the gate, the method comprising: forming a field oxide film on the semiconductor substrate, sequentially forming an insulating film, a conduction film and another insulating film to predetermined thicknesses, and selectively etching the films such that the semiconductor substrate is exposed at a portion thereof disposed at a source/drain region; implanting impurity ions in the exposed portion of the semiconductor substrate, thereby forming the source/drain; forming a conduction film and an insulating film over the entire exposed surface obtained after the formation of the source/drain, and selectively etching the films, thereby forming a spacer disposed over the source/drain; and forming another insulating film and a polysilicon film over the entire exposed surface including said spacers and selectively etching the films, thereby forming a gate insulating film and the gate.
Claim 3
Dependent Claim 29 words
A method in accordance with claim 1, wherein the polysilicon film and the insulating film both constituting the gate are a doped polysilicon film and a silicide film, respectively.
Claim 4
Dependent Claim 19 words
A method in accordance with claim 1, wherein the conduction film constituting the spacer is a doped polysilicon film.
Claim 5
Dependent Claim 22 words
A method in accordance with claim 1, wherein the insulating film constituting the spacer is formed using a low temperature deposition process.
Claim 6
Dependent Claim 94 words
A method in accordance with claim 1, wherein the method comprises the steps of: forming a planarizing insulating film over the entire exposed surface of the resulting structure obtained after the formation of the gate; selectively etching the planarizing insulating film and the insulating film disposed over the conduction film being in contact with the spacer disposed over the source/drain, thereby exposing a predetermined portion of the conduction film being in direct contact with the source/drain; and forming a metal film on the exposed portion of the conduction film, thereby forming a metal wiring.
Claim 7
Dependent Claim 52 words
A method in accordance with claim 5, wherein the step of forming the planarizing insulating film comprises the steps of: forming an oxide film over the entire exposed surface of the resulting structure obtained after the formation of the gate; and forming a boro-phosphor-silicate-glass film for a planarization over the oxide film.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-05-17 2002-11-16 2003-05-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-05-17 2006-11-16 2007-05-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-05-17 2010-11-16 2011-05-18 $7700.00 Window Closed / Lapsed

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