Fet with gate spacer

Claim 1

A method of semiconductor integrated circuit fabrication comprising: forming a gate stack upon a substrate; forming a first material layer upon said gate stack and upon said substrate; forming a second material layer upon said first material layer; forming a third material layer upon said second material layer; anisotropically etching said third layer to form a first spacer and then etching said second layer to form a second spacer underlying said first spacer; exposing said substrate to a first dopant species, said first and second spacers serving to at least partially block or absorb some of said first dopant species thereby creating a deep junction; and characterized by removing said first spacer; exposing said substrate to a second dopant species, said second spacer serving to at least partially block or absorb some of said second dopant species, thereby creating a shallow junction which taken in combination with said deep junction forms a lightly doped drain junction; depositing a metal upon said substrate, said metal covering said deep junction; said second spacer serving to prevent said metal from covering said shallow junction; forming a metal silicide, said silicide covering said deep junction and not contacting said shallow junction; and said first material layer having been removed to expose a portion of said substrate surface prior to said metal deposition step.

Claim 2

A method of semiconductor integrated circuit fabrication comprising: forming a gate stack upon a substrate; forming a first material layer upon said gate stack and upon said substrate; forming a second material layer upon said first material layer; forming a third material layer upon said second material layer; anisotropically etching said third layer to form a first spacer and then etching said second layer to form a second spacer underlying said first spacer; exposing said substrate to a first dopant species, said first and second spacers serving to at least partially block or absorb some of said first dopant species thereby creating a deep junction; and characterized by removing said first spacer; exposing said substrate to a second dopant species, said second spacer serving to at least partially block or absorb some of said second dopant species, thereby creating a shallow junction which taken in combination with said deep junction forms a lightly doped drain junction; depositing a metal upon said substrate, said metal covering said deep junction; said second spacer serving to prevent said metal from covering said shallow junction; forming a metal silicide, said silicide covering said deep junction and not contacting said shallow junction; and said first material layer having been removed to expose a portion of said substrate surface prior to said metal deposition step.