Process for forming titanium silicide local interconnect

Claim 2

A process for forming a metal silicide local interconnect between contact points separated by a dielectric insulator on an integrated circuit comprising: forming a first layer of metal on said insulator; forming a layer of silicon on said metal; masking and etching said silicon layer to form a silicon strip connecting said contact points, wherein said silicon strip includes a top and substantially vertical sidewalls; forming an overlying second layer of metal, wherein said second metal layer covers said top and sidewalls; heating said metal and silicon to form a nonsilicidized metal over a strip of metal silicide; and removing said nonsilicidized metal.

Claim 3

The process of claim 1 further comprising: forming a layer of oxide on said silicon prior to masking and etching; wherein said metal silicide strip includes an oxide cap.

Claim 4

The process of claim 1 wherein said dielectric insulator comprises field oxide.

Claim 5

The process of claim 1 wherein said nonsilicidized metal is a metal nitride or nonreacted metal.

Claim 6

The process of claim 1 wherein said removing step includes a selective etch of said nonsilicidized metal.

Claim 7

The process of claim 1 wherein said metal is a transition metal.

Claim 8

The process of claim 6 wherein said transition metal is titanium, cobalt, platinum, palladium, molybdenum, tantalum or nickel.

Claim 9

A process for forming a metal silicide local interconnect between contact points separated by a dielectric insulator on an integrated circuit comprising: forming a first layer of metal on said insulator; forming a layer of silicon on said metal; masking and etching said silicon layer to form a silicon strip connecting said contact points; forming an overlying second layer of metal; heating said metal and silicon to form a nonsilicidized metal over a strip of metal silicide; and removing said nonsilicidized metal; wherein said first layer of metal is formed into a layered strip with said silicon strip during said masking and etching step.

Claim 10

A process for forming a metal silicide local interconnect between contact points separated by a dielectric insulator on an integrated circuit comprising: forming a first layer of metal on said insulator; forming a layer of silicon on said metal; masking and etching said silicon layer to form a silicon strip connecting said contact points; forming an overlying second layer of metal; heating said metal and silicon to form a nonsilicidized metal over a strip of metal silicide; and removing said nonsilicidized metal; wherein said first layer of metal is formed into a layered strip with said silicon strip during said masking and etching step.

Claim 11

The process of claim 8 wherein said layered strip includes a top and substantially vertical sidewalls and wherein said second metal layer covers said top and sidewalls.

Claim 12

A process for forming a titanium silicide local interconnect between contact points separated by a dielectric insulator on an integrated circuit comprising: forming a first layer of titanium on said insulator; forming a layer of silicon on said titanium; masking and etching said silicon layer to form a silicon strip connecting said contact points, wherein said silicon strip includes a top and sidewalls; forming a second layer of titanium on said top and sidewalls of said silicon strip; heating said second titanium layer and silicon strip to form a titanium nitride coating over a strip of titanium silicide; removing said coating by a selective etch; and forming a glass layer over said titanium silicide strip.

Claim 13

A process for forming a titanium silicide local interconnect between contact points separated by a dielectric insulator on an integrated circuit comprising: forming a first layer of titanium on said insulator; forming a layer of silicon on said titanium; masking and etching said silicon layer to form a silicon strip connecting said contact points, wherein said silicon strip includes a top and sidewalls; forming a second layer of titanium on said top and sidewalls of said silicon strip; heating said second titanium layer and silicon strip to form a titanium nitride coating over a strip of titanium silicide; removing said coating by a selective etch; and forming a glass layer over said titanium silicide strip.

Claim 14

The process of claim 10 further comprising: reheating said titanium silicide strip after removing said coating to a temperature greater than the temperature of said heating step.

Claim 15

The process of claim 11 further comprising: providing an overlying metalization layer with a contact to said titanium silicide through an opening in said glass.

Claim 16

The process of claim 10 further comprising: forming a layer of oxide on said silicon prior to masking and etching said silicon layer; wherein said silicon strip includes an oxide cap.

Claim 17

The process of claim 13 further comprising: reheating said oxide capped, titanium silicide strip after removing said coating to a temperature greater than the temperature of said heating step.

Claim 18

The process of claim 14 further comprising: providing an overlying metalization layer with a contact to said titanium silicide through an opening in said glass and oxide cap.

Claim 19

The process of claim 10 further comprising: covering said layer of silicon and said contact points and dielectric insulator with a layer of oxide.

Claim 20

A process for forming a titanium silicide local interconnect between contact points separated by a dielectric insulator on an integrated circuit comprising: forming a first layer of titanium on said insulator; forming a layer of silicon on said titanium; masking and etching said silicon layer to form a silicon strip connecting said contact points, wherein said silicon strip includes a top and sidewalls; forming a second layer of titanium on said top and sidewalls of said silicon strip; heating said second titanium layer and silicon strip to form a titanium nitride coating over a strip of titanium silicide; removing said coating by a selective etch; and forming a glass layer over said titanium silicide strip; wherein said first layer of titanium is formed into a layered strip with said silicon strip during said masking and etching step.

Claim 21

A process for forming a titanium silicide local interconnect between contact points separated by a dielectric insulator on an integrated circuit comprising: forming a first layer of titanium on said insulator; forming a layer of silicon on said titanium; masking and etching said silicon layer to form a silicon strip connecting said contact points, wherein said silicon strip includes a top and sidewalls; forming a second layer of titanium on said top and sidewalls of said silicon strip; heating said second titanium layer and silicon strip to form a titanium nitride coating over a strip of titanium silicide; removing said coating by a selective etch; and forming a glass layer over said titanium silicide strip; wherein said first layer of titanium is formed into a layered strip with said silicon strip during said masking and etching step.

Claim 22

The process of claim 17 further comprising: reheating said titanium silicide strip after removing said coating to a temperature greater than the temperature of said heating step.

Claim 23

The process of claim 18 further comprising: providing an overlying metalization layer with a contact to said titanium silicide through an opening in said glass.

Claim 24

A process for forming a titanium silicide local interconnect between contact points separated by a dielectric insulator on an integrated circuit comprising: forming a first layer of titanium on said insulator; forming a layer of silicon on said titanium; masking and etching said silicon layer to form a silicon strip connecting said contact points, wherein said silicon strip includes a top and sidewalls; forming a second layer of titanium on said top and sidewalls of said silicon strip; heating said second titanium layer and silicon strip to form a titanium nitride coating over a strip of titanium silicide; removing said coating by a selective etch; and forming a glass layer over said titanium silicide strip; forming a layer of oxide on said silicon prior to masking and etching said silicon layer; wherein said silicon strip includes an oxide cap; and wherein said first layer of titanium is formed into a layered strip with said oxide capped, silicon strip during said masking and etching step.

Claim 25

A process for forming a titanium silicide local interconnect between contact points separated by a dielectric insulator on an integrated circuit comprising: forming a first layer of titanium on said insulator; forming a layer of silicon on said titanium; masking and etching said silicon layer to form a silicon strip connecting said contact points, wherein said silicon strip includes a top and sidewalls; forming a second layer of titanium on said top and sidewalls of said silicon strip; heating said second titanium layer and silicon strip to form a titanium nitride coating over a strip of titanium silicide; removing said coating by a selective etch; and forming a glass layer over said titanium silicide strip; forming a layer of oxide on said silicon prior to masking and etching said silicon layer; wherein said silicon strip includes an oxide cap; and wherein said first layer of titanium is formed into a layered strip with said oxide capped, silicon strip during said masking and etching step.

Claim 26

The process of claim 20 further comprising: reheating said oxide capped, titanium silicide strip after removing said coating to a temperature greater than the temperature of said heating step.

Claim 27

The process of claim 21 further comprising: providing an overlying metalization layer with a contact to said titanium silicide through an opening in said glass and oxide cap.

Claim 28

A process for forming a metal silicide strip on an integrated circuit having a plurality of source and drain regions, comprising: forming a silicon strip overlying first metal, wherein said silicon strip includes a top and substantially vertical sidewalls; coating said silicon strip including said top and substantially vertical sidewalls with second metal; and heating the coated strip to form metal silicide within at least one of the plurality of source and drain regions.

Claim 29

A process for forming a metal silicide strip on an integrated circuit having a plurality of source and drain regions, comprising: forming a silicon strip overlying first metal, wherein said silicon strip includes a top and substantially vertical sidewalls; coating said silicon strip including said top and substantially vertical sidewalls with second metal; and heating the coated strip to form metal silicide within at least one of the plurality of source and drain regions.

Claim 30

A process for forming a metal silicide strip on an integrated circuit having a plurality of source and drain regions, comprising: forming a silicon strip overlying first metal; coating said silicon strip with second metal; and heating the coated strip to form metal silicide within at least one of the plurality of source and drain regions, wherein said first metal is formed into a layered strip with said silicon strip during said forming step.

Claim 31

A process for forming a metal silicide strip on an integrated circuit having a plurality of source and drain regions, comprising: forming a silicon strip overlying first metal; coating said silicon strip with second metal; and heating the coated strip to form metal silicide within at least one of the plurality of source and drain regions, wherein said first metal is formed into a layered strip with said silicon strip during said forming step.

Claim 32

A process for forming a metal silicide strip on an integrated circuit comprising: forming an oxide capped silicon strip overlying first metal, wherein said silicon strip includes a top and substantially vertical sidewalls; coating said oxide capped silicon strip with second metal, wherein said second metal layer covers said sidewalls; heating the coated strip to form an oxide capped metal silicide strip coated with nonsilicidized metal; and removing said nonsilicidized metal.

Claim 33

A process for forming a metal silicide strip on an integrated circuit comprising: forming an oxide capped silicon strip overlying first metal, wherein said silicon strip includes a top and substantially vertical sidewalls; coating said oxide capped silicon strip with second metal, wherein said second metal layer covers said sidewalls; heating the coated strip to form an oxide capped metal silicide strip coated with nonsilicidized metal; and removing said nonsilicidized metal.

Claim 34

A process for forming a metal silicide strip on an integrated circuit comprising: forming an oxide capped silicon strip overlying first metal; coating said oxide capped silicon strip with second metal; heating the coated strip to form an oxide capped metal silicide strip coated with nonsilicidized metal; and removing said nonsilicidized metal; wherein said first metal is formed into a layered strip with said oxide capped silicon strip during said forming step.

Claim 35

A process for forming a metal silicide strip on an integrated circuit comprising: forming an oxide capped silicon strip overlying first metal; coating said oxide capped silicon strip with second metal; heating the coated strip to form an oxide capped metal silicide strip coated with nonsilicidized metal; and removing said nonsilicidized metal; wherein said first metal is formed into a layered strip with said oxide capped silicon strip during said forming step.

Claim 36

In the manufacture of an electronic integrated circuit, a process for forming a local interconnect between contact points comprising the following steps: forming a strip of silicon upon a metal, which strip includes a top and substantially vertical sidewalls and extends between the contact points; applying a barrier metal to protect both the silicon strip, including the top and substantially vertical sidewalls, and the metal from ambient gases; heating the silicon strip, the metal, and the barrier metal so that the silicon, the barrier metal and the metal form a silicide for use in said local interconnect.

Claim 37

In the manufacture of an electronic integrated circuit, a process for forming a local interconnect between contact points comprising the following steps: forming a strip of silicon upon a metal, which strip includes a top and substantially vertical sidewalls and extends between the contact points; applying a barrier metal to protect both the silicon strip, including the top and substantially vertical sidewalls, and the metal from ambient gases; heating the silicon strip, the metal, and the barrier metal so that the silicon, the barrier metal and the metal form a silicide for use in said local interconnect.