US6028816A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor
Assignee: Socionext Inc
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Filing: 1997-09-05
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Granted: 2000-02-22
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Expires: 2017-09-05
Abstract
Abstract A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.
Inventors
- 👤 Yoshihiro Takemae
- 👤 Masao Taguchi
- 👤 Yasurou Matsuzaki
- 👤 Hiroyoshi Tomita
- 👤 Hirohiko Mochizuki
- 👤 Atsushi Hatakeyama
- 👤 Yoshinori Okajima
- 👤 Masao Nakano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:06
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045; G11C7/1051; G11C7/1057; G11C7/1072; G11C7/1078; G11C7/1087; G11C7/1093; G11C7/22; G11C7/222; G11C7/225; H03K; H03K5/00; H03K5/13; H03K5/133; H03K5/135; H03L7/081; H03L7/0812; H03L7/0814; G11C2207/00; G11C2207/10; G11C2207/108
Claims Analysis
Total Claims: 69
Claim 1
Independent Claim
83 words
A semiconductor device system comprising: a driving-end semiconductor device outputting a clock and an output signal in synchronism with said clock; and a receiving-end semiconductor device receiving said clock and said output signal as an input signal said receiving-end semiconductor device including: an input circuit for receiving said input signal and latching said input signal in synchronism with an internal clock; and an input timing adjusting circuit receiving said clock and outputting said internal clock for adjusting a phase of said internal clock.
Claim 2
Dependent Claim
83 words
A semiconductor device system comprising: a driving-end semiconductor device outputting a clock and an output signal in synchronism with said clock; and a receiving-end semiconductor device receiving said clock and said output signal as an input signal said receiving-end semiconductor device including: an input circuit for receiving said input signal and latching said input signal in synchronism with an internal clock; and an input timing adjusting circuit receiving said clock and outputting said internal clock for adjusting a phase of said internal clock.
Claim 3
Dependent Claim
108 words
A semiconductor device system according to claim 1, wherein said input timing adjusting circuit includes: a delay circuit with a selectable delay amount for delaying the internal clock generated on the basis of said clock received and producing said internal clock as an input timing clock; a phase comparator circuit for judging the phase of said input timing clock and said input signal; and a delay control circuit for changing the delay amount of said delay circuit in such a manner that said input timing clock assumes a predetermined phase relation with respect to said input signal on the basis of the judgement of said phase comparator circuit.
Claim 4
Dependent Claim
59 words
A semiconductor device system according to claim 2, wherein: said receiving-end semiconductor device includes a shift clock generating circuit for displacing said input timing clock by said predetermined phase and generating a shift clock changing in phase with said input signal; and said phase comparator circuit compares the phase of said shift clock with that of said input signal.
Claim 5
Dependent Claim
92 words
A semiconductor device system according to claim 2, wherein: said receiving-end semiconductor device includes a shift clock generating circuit for generating from said internal clock two original shift clocks displaced by a predetermined amount of phase from each other; said delay circuit outputs said two original shift clocks delayed by the same amount, one shift clock as said input timing clock and the other shift clock as an output to said phase comparator circuit; and said phase comparator circuit compares the phase of said shift clocks with that of said input signal.
Claim 6
Dependent Claim
55 words
A semiconductor device system according to claim 2, wherein: said phase comparator circuit includes a change information detection circuit for detecting whether said input signal has changed and, if changed, the direction of change, and means for judging the phase on the basis of the result of detection by said change information change detection circuit.
Claim 7
Dependent Claim
59 words
A semiconductor device system according to claim 2, further comprising a minimum period change detection circuit for detecting that said input signal has changed continuously during the immediately preceding two clock cycles; wherein said delay control circuit changes the delay amount of said delay circuit only when said input signal continuously changes in the immediately preceding two clock cycles.
Claim 8
Dependent Claim
89 words
A semiconductor device system according to claim 2, further comprising: a timing correction circuit for selecting whether the timing of retrieval by said signal input circuit is delayed by a predetermined amount; and an immediately preceding change detection circuit for detecting that said input signal has changed in the immediately preceding clock cycle; wherein in the case when said input signal fails to change in the immediately preceding clock cycle, the retrieval timing of said signal input circuit is delayed by a predetermined amount by said timing correction circuit.
Claim 9
Dependent Claim
74 words
A semiconductor device system according to claim 1, wherein: said receiving-end semiconductor device receiving a plurality of input signals including said input signal, said receiving-end semiconductor device includes a plurality of input circuits including said input circuit for receiving said plurality of input signals and a plurality of input timing adjusting circuits each of which corresponds to said input timing adjusting circuit, and each input timing adjusting circuit is provided for each input circuit.
Claim 10
Dependent Claim
45 words
A semiconductor device system according to claim 8, wherein: said receiving-end semiconductor device further includes an inter-signal timing adjusting circuit for detecting the phase difference between the output signals of said plurality of input circuits and adjusting said output signals in phase with each other.
Claim 11
Dependent Claim
40 words
A semiconductor device system according to claim 9, wherein: said inter-signal timing adjusting circuit detects the phase difference between the output signals of said plurality of signal input circuits on the basis of the control value of delay control circuit.
Claim 12
Dependent Claim
52 words
A semiconductor device system according to claim 1, wherein: a predetermined period after starting said semiconductor device system is set as a receiving timing adjust mode for adjusting said input timing adjusting circuit, followed by a normal operation mode, said input timing adjusting circuit being adjusted also in said normal operation mode.
Claim 13
Dependent Claim
77 words
A semiconductor device system according to claim 1, wherein: said semiconductor device system has a normal mode and a receiving timing adjust mode for adjusting the timing of receiving said input signal in said receiving-end semiconductor device; and said input timing adjusting circuit changes the phase of said internal clock supplied to said input circuit in said receiving timing adjust mode and holds said phase of said clock supplied to said input circuit in said normal mode.
Claim 14
Dependent Claim
79 words
A semiconductor device system according to claim 2, wherein: the modes of operation of said semiconductor device system include a normal mode and a receiving timing adjust mode for adjusting the timing of receiving said input signal in said receiving-end semiconductor device; and said delay control circuit changes the delay amount on the basis of the result of comparison of said phase comparator circuit in said receiving timing adjust mode, and holds the delay amount in said normal mode.
Claim 15
Dependent Claim
44 words
A semiconductor device system according to claim 13, wherein: said driving-end semiconductor device issues a mode indication signal for indicating the receiving timing adjust mode for the input signal; and said receiving-end semiconductor device includes a mode register/decoder for recognizing said mode indication signal.
Claim 16
Dependent Claim
46 words
A semiconductor device system according to claim 13, wherein: said driving-end semiconductor device outputs an adjust output signal changing at a predetermined period in said receiving timing adjust mode at a timing displaced by a predetermined amount of phase from the timing for said normal mode.
Claim 17
Dependent Claim
51 words
A semiconductor device system according to claim 13, wherein: said driving-end semiconductor device includes an output timing adjusting circuit for comparing the phase of said output signal produced from said driving-end semiconductor device with that of said clock and adjusting the phase of said output signal with respect to said clock.
Claim 18
Dependent Claim
74 words
A semiconductor device system according to claim 13, wherein: said receiving-end semiconductor device receiving a plurality of input signals including said input signal, said receiving-end semiconductor device includes a plurality of input circuits including said input circuit for receiving said plurality of input signals and a plurality of input timing adjusting circuits each of which corresponds to said input timing adjusting circuit, and each input timing adjusting circuit is provided for each input circuit.
Claim 19
Dependent Claim
43 words
A semiconductor device system according to claim 17, wherein: said receiving-end semiconductor device includes an inter-signal timing adjusting circuit for detecting the phase difference between the output signals of said plurality of input circuits and adjusting said output signals into the same phase.
Claim 20
Dependent Claim
53 words
A semiconductor device system according to claim 18, wherein: said inter-signal timing adjusting circuit performs the adjusting operation on the basis of a combination of said input signals having a predetermined signal pattern input during said receiving timing adjust mode, and maintains the adjusted value after completion of said receiving timing adjust mode.
Claim 21
Dependent Claim
43 words
A semiconductor device system according to claim 19, wherein: a predetermined signal pattern of said input signals input during said receiving timing adjust mode assumes a different logical value only during a specific one of the cycles where the same logical value continues.
Claim 22
Dependent Claim
61 words
A semiconductor device system according to claim 13, wherein: said receiving-end semiconductor device receives a plurality of input signals including said input signal, some of said input signals having a long period and other of said input signals having a short period, and said mode indication signal is a combination of the values of said input signals of a long period.
Claim 23
Dependent Claim
37 words
A semiconductor device system according to claim 19, wherein: said input signal having said predetermined signal pattern is input for a predetermined length of time even after indication of the end of said receiving timing adjust mode.
Claim 24
Dependent Claim
68 words
A semiconductor device system according to claim 18, wherein: said input signal includes a combination of a plurality of signals in continuous cycles; said input circuit includes a parallel conversion circuit for retrieving said input signals and converting said plurality of signals of continuous cycles into parallel signals; and said inter-signal timing adjusting circuit adjusts said combination of outputs of said parallel conversion circuits into the same phase.
Claim 25
Dependent Claim
23 words
A semiconductor device system according to claim 23, wherein: a plurality of said input signals are input during one cycle of said clock.
Claim 26
Dependent Claim
84 words
A semiconductor device, comprising: an input circuit for receiving an input signal and latching said input signal in synchronism with an internal clock; and an input timing adjusting circuit receiving a clock and outputting said internal clock for adjusting a phase of said internal clock, wherein said input timing adjusting circuit includes a feedback circuit receiving said internal clock and generating a timing control signal, said adjusting of the phase of said internal clock is carried out in response to the timing control signal.
Claim 27
Dependent Claim
84 words
A semiconductor device, comprising: an input circuit for receiving an input signal and latching said input signal in synchronism with an internal clock; and an input timing adjusting circuit receiving a clock and outputting said internal clock for adjusting a phase of said internal clock, wherein said input timing adjusting circuit includes a feedback circuit receiving said internal clock and generating a timing control signal, said adjusting of the phase of said internal clock is carried out in response to the timing control signal.
Claim 28
Dependent Claim
89 words
A semiconductor device according to claim 25, wherein said input timing adjusting circuit includes: a delay circuit for delaying said clock to produce said internal clock; a phase comparator circuit for comparing the phase of said internal clock and the phase of said input signal; and a delay control circuit for controlling a delay amount of said delay circuit in response to a comparison result of said phase comparator circuit in such a manner that said internal clock has a predetermined phase relation with respect to said input signal.
Claim 29
Dependent Claim
57 words
A semiconductor device according to claim 26, further comprising: a shift clock generating circuit for generating a shift clock changing in phase with said input signal by displacing said input timing clock by a predetermined amount of phase; wherein said phase comparator circuit compares the phase of said shift clock with the phase of said input signal.
Claim 30
Dependent Claim
100 words
A semiconductor device according to claim 27, further comprising a shift clock generating circuit for generating two original shift clocks displaced by said predetermined phase relation from each other from said internal clock; wherein said delay circuit delays each of said two original shift clocks by the same amount, one of said original shift clocks being output as said input timing clock, the other of said original shift clocks being output to said phase comparator circuit as a shift clock; and wherein said phase comparator circuit compares the phase of said shift clock with the phase of said input signal.
Claim 31
Dependent Claim
154 words
A semiconductor device according to claim 27, wherein said shift clock generating circuit includes: a plurality of stages of shift delay circuits with the same selectable delay amount, the output of a preceding stage being applied to the following stage, said input timing clock being applied to the initial stage; a clock phase comparator circuit for comparing the phase of the output in the last stage of said shift delay circuits with the phase of said input timing clock; and a delay control circuit for controlling the delay amount of said plurality of stages of said shift delay circuits in such a manner that the phase of the output from said last stage coincides with the phase of said input timing clock on the basis of the result of comparison at said clock phase comparator circuit; and the output from a predetermined stage of said shift delay circuits is output as said shift clock.
Claim 32
Dependent Claim
166 words
A semiconductor device according to claim 28, wherein said shift clock generating circuit includes: a plurality of stages of shift delay circuits with the same selectable delay amount, the output of a preceding stage being applied to the following stage, said internal clock being applied to the initial stage; a clock phase comparator circuit for comparing the phase of the output in the last stage of said shift delay circuits with the phase of said input timing clock; and a delay control circuit for controlling the delay amount of said plurality of stages of said shift delay circuits in such a manner that the phase of the output from said last stage coincides with the phase of said input timing clock on the basis of the result of comparison at said clock phase comparator circuit; and the output from a predetermined stage of said shift delay circuits and said internal clock or the output from the last stage are output as said two original shift clocks.
Claim 33
Dependent Claim
120 words
A semiconductor device according to claim 27, wherein said phase comparator circuit includes: a dummy latch for receiving said input signal in synchronism with said shift clock; a change information detection circuit for detecting whether the change of said input signal in the vicinity of an area where said dummy latch receives said input signal is a rising edge or a falling edge; and a phase judge circuit for judging the direction in which the phase of said shift clock is changed with respect to the phase of said input signal only when said input signal is changed, on the basis of the value received by said dummy latch and the result of detection at said change information detection circuit.
Claim 34
Dependent Claim
85 words
A semiconductor device according to claim 31, wherein said change information detection circuit includes: a latch for receiving said input signal before said dummy latch receives said input signal; and a holding circuit for holding the value received by said latch for a predetermined length of time after said latch receives the next input signal; wherein said phase judge circuit detects whether said input signal has changed and, if changed, the direction of said change, from the value of said latch and said holding circuit.
Claim 35
Dependent Claim
29 words
A semiconductor device according to claim 32, wherein said holding circuit is a delay latch for receiving the output of said latch at the same timing as said latch.
Claim 36
Dependent Claim
22 words
A semiconductor device according to claim 32, wherein said holding circuit is a delay circuit for delaying the output of said latch.
Claim 37
Dependent Claim
19 words
A semiconductor device according to claim 32, wherein said latch constitutes said input circuit for retrieving said input signal.
Claim 38
Dependent Claim
59 words
A semiconductor device according to claim 26, further comprising a minimum period change detection circuit for detecting that said input signal has changed continuously in the immediately preceding two clock cycles; wherein said delay control circuit changes the delay amount of said delay circuit only when said input signal has changed continuously in the immediately preceding two clock cycles.
Claim 39
Dependent Claim
104 words
A semiconductor device according to claim 36, wherein said minimum period change detection circuit includes: a first delay latch for receiving the output of a latch of said input circuit for receiving said input signal, at the same timing as said latch; a second delay latch for receiving the output of said first delay latch at the same timing as said latch; and a minimum period change judging circuit for judging that said input signal has continuously changed in the immediately preceding two clock cycles when all the outputs of said latch, said first delay latch and said second delay latch undergo a change.
Claim 40
Dependent Claim
76 words
A semiconductor device according to claim 32, further comprising a minimum period change detection circuit for detecting that said input signal has continuously changed in the immediately preceding two clock cycles; wherein said delay control circuit changes the delay amount of said delay circuit only when said input signal changes continuously in the immediately preceding two clock cycles; and wherein said change information detection circuit and said minimum period change detection circuit partially share each other.
Claim 41
Dependent Claim
92 words
A semiconductor device according to claim 25, further comprising: a timing correction circuit for selecting whether or not the timing of retrieval at said input circuit is to be delayed by a predetermined amount; and an input signal change detection circuit for detecting that said input signal has changed in the immediately preceding clock cycle; wherein in the case where said input signal fails to change in the immediately preceding clock cycle, the timing of retrieval at said signal input circuit is delayed by a predetermined amount by said timing correction circuit.
Claim 42
Dependent Claim
74 words
A semiconductor device according to claim 39, wherein said input signal change detection circuit includes: a delay latch for receiving the output of a latch of said input circuit for receiving said input signal, at the same timing as said latch; and a circuit for judging that said input signal fails to change in the immediately preceding clock cycle when the output of said latch is identical to the output of said delay latch.
Claim 43
Dependent Claim
112 words
A semiconductor device according to claim 38, further comprising: a timing correction circuit for selecting whether or not the retrieval timing at said signal input circuit is to be delayed by a predetermined amount; and an input signal change detection circuit for detecting that said input signal has changed in the immediately preceding clock cycle; wherein in the case where said input signal fails to change in the immediately preceding clock cycle, said timing correction circuit delays the retrieval timing of said signal input circuit by a predetermined amount; and wherein said change information detection circuit, said minimum period change detection circuit and said input signal change detection circuit partially share circuitry.
Claim 44
Dependent Claim
87 words
A semiconductor device according to claim 25, wherein said semiconductor device receives a plurality of input signals including said input signal, said semiconductor device comprises a plurality of input circuits including said input circuit for receiving said plurality of input signals, said input timing adjusting circuit is provided for each of said input circuits; and said semiconductor device further comprises an inter-timing adjusting circuit for detecting the phase difference between the output signals of said signal input circuits and adjusting said output signals into the same phase.
Claim 45
Dependent Claim
141 words
A semiconductor device according to claim 42, wherein said input timing adjusting circuit includes: a delay circuit with a selectable delay amount for receiving the internal clock generated based on the clock received and producing said internal clock as an input timing clock; a phase comparator circuit for judging the phase of the input timing clock and the phase of said input signal; and a delay control circuit for changing the delay amount of said delay circuit in such a manner that said input timing clock has a predetermined phase relation with respect to said input signal on the basis of the result of the comparison at said phase comparator circuit; said inter-signal timing adjusting circuit detects the phase difference between the output signals of said signal input circuits on the basis of a control value of said delay control circuit.
Claim 46
Dependent Claim
55 words
A semiconductor device according to claim 25, wherein a predetermined period after activating said semiconductor device constitutes a receiving timing adjust mode for adjusting said input timing adjusting circuit, the subsequent period constituting a normal operation mode, and the adjustment by said input timing adjusting circuit is carried out also in said normal operation mode.
Claim 47
Dependent Claim
68 words
A semiconductor device according to claim 26, wherein said semiconductor device has a normal mode and a receiving timing adjust mode for adjusting the retrieval timing of said input signal; and wherein said delay control circuit changes the delay amount on the basis of the result of comparison of said phase comparator circuit in the receiving timing adjust mode and holds the delay amount in said normal mode.
Claim 48
Dependent Claim
24 words
A semiconductor device according to claim 45, further comprising a mode register/decoder for recognizing a mode indication signal indicating said receiving timing adjust mode.
Claim 49
Dependent Claim
81 words
A semiconductor device according to claim 45, further comprising a clock generating circuit for generating the internal clock and a shift clock for shifting said internal clock by a predetermined amount of phase on the basis of said received clock, and applying selected one of said internal clock and said shift clock to said delay circuit; wherein said clock generating circuit selectively outputs said internal clock in said normal mode and outputs said shift clock in said receiving timing adjust mode.
Claim 50
Dependent Claim
122 words
A semiconductor device according to claim 47, wherein said phase comparator circuit includes: a dummy latch for receiving said input signal in synchronism with said shift clock; a change information detection circuit for detecting whether the change of said input signal in the vicinity of a point of retrieval of said input signal by said dummy latch is a rising edge or a falling edge; and a phase judge circuit for judging the direction in which the phase of said shift clock is changed with respect to the phase of said input signal only when said input signal has changed, on the basis of the value retrieved by said dummy latch and the result of detection at said change information detection circuit.
Claim 51
Dependent Claim
86 words
A semiconductor device according to claim 48, wherein said change information detection circuit includes: a latch for receiving said input signal before or after said dummy latch retrieves said input signal; a holding circuit for holding the value received by said latch for a predetermined length of time after said latch receives the next input signal; wherein said phase judge circuit detects whether said input signal has changed and, if changed, the direction of said change, from the value of said latch and said holding circuit.
Claim 52
Dependent Claim
20 words
A semiconductor device according to claim 49, wherein said input latch constitutes said input circuit for retrieving said input signal.
Claim 53
Dependent Claim
92 words
A semiconductor device according to claim 45, wherein said semiconductor device receives a plurality of input signals including said input signal, said semiconductor device comprises a plurality of input circuits including said input circuit for receiving said plurality of input signals, said input timing adjusting circuit is provided for each of said input circuits; said semiconductor device further comprises an inter-signal timing adjusting circuit for detecting the phase difference between the output signals of said input circuits and adjusting said output signals of said plurality of input circuits into the same phase.
Claim 54
Dependent Claim
59 words
A semiconductor device according to claim 51, wherein said inter-signal timing adjusting circuit includes: a common effective period detection circuit for detecting a period during which all the output signals of said input circuits have the same cycle; and a plurality of latch circuits for latching the output signal of said input circuits during said common effective signal period.
Claim 55
Dependent Claim
63 words
A semiconductor device according to claim 51, wherein said inter-signal timing adjusting circuit includes: a signal delay circuit for delaying the output signals of said input circuits; and a delay control register for detecting the most delayed signal among the output signals of said input circuits and controlling the delay amount of said signal delay circuit in conformance with said most delayed signal.
Claim 56
Dependent Claim
76 words
A semiconductor device according to claim 51, further comprising a mode register/decoder for recognizing a mode indication signal supplied from an external source for indicating the receiving timing adjust mode for the input signal; wherein said input timing adjusting circuit performs the adjustment on the basis of a combination of said input signals having a predetermined signal pattern input during said receiving timing adjust mode, and maintains an adjusted value after said receiving timing adjust mode.
Claim 57
Dependent Claim
82 words
A semiconductor device according to claim 52, further comprising a mode register/decoder for recognizing a mode indication signal supplied from an external source for indicating the receiving timing adjust mode for the input signal; wherein said input timing adjusting circuit and said inter-signal timing adjusting circuit perform the adjustment on the basis of a combination of said input signals having a predetermined signal pattern input during said receiving timing adjust mode, and maintains an adjusted value after said receiving timing adjust mode.
Claim 58
Dependent Claim
94 words
A semiconductor device according to claim 55, wherein the predetermined signal pattern of said input signal input during said receiving timing adjust mode assumes a different logic value only in a specific one of the cycles in which the same logic value continues; and wherein said common effective period detection circuit includes a gate for calculating the logic product of the output signals of said input circuits, and detects the period during which all the output signals of the input circuits have the same cycle, on the basis of the output of said gate.
Claim 59
Dependent Claim
82 words
A semiconductor device according to claim 53, further comprising a mode register/decoder for recognizing a mode indication signal supplied from an external source for indicating the receiving timing adjust mode for the input signal; wherein said input timing adjusting circuit and said inter-signal timing adjusting circuit perform the adjustment on the basis of a combination of said input signals having a predetermined signal pattern input during said receiving timing adjust mode, and maintains an adjusted value after said receiving timing adjust mode.
Claim 60
Dependent Claim
48 words
A semiconductor device according to claim 56, wherein said input signals include at least one of two kinds of signals of a short period and a long period, and wherein said mode indication signal is a combination of the values of said input signals of a long period.
Claim 61
Dependent Claim
22 words
A semiconductor device according to claim 56, wherein said mode indication signal is applied by way of a dedicated input signal terminal.
Claim 62
Dependent Claim
36 words
A semiconductor device according to claim 58 59, wherein said input signal having said predetermined signal pattern is applied during a predetermined length of time after the end of said receiving timing adjust mode is indicated.
Claim 63
Dependent Claim
35 words
A semiconductor device according to claim 51, further comprising an internal circuit supplied with output signals from said input circuits; wherein said inter-signal timing adjusting circuit is arranged in the vicinity of said internal circuit.
Claim 64
Dependent Claim
22 words
A semiconductor device according to claim 61, wherein said input timing adjusting circuit is arranged in the vicinity of said internal circuit.
Claim 65
Dependent Claim
21 words
A semiconductor device according to claim 51, wherein a plurality of said input timing adjusting circuits are arranged in a cluster.
Claim 66
Dependent Claim
45 words
A semiconductor device according to claim 63, wherein said input timing adjusting circuit includes a delay circuit for adjusting the phase of said clock; and wherein said plurality of said input timing adjusting circuits arranged in a cluster share a part of said delay circuit.
Claim 67
Dependent Claim
64 words
A semiconductor device according to claim 51, wherein said input circuit includes a parallel conversion circuit for converting two continuous said input signals into parallel signals after retrieving said input signals; and wherein said inter-signal timing adjusting circuit adjusts the of output signals said parallel conversion circuit in such a manner that the signals of the same cycle are in phase with each other.
Claim 68
Dependent Claim
71 words
A semiconductor device according to claim 51, wherein said input signals constitute signal sets each having a plurality of cycles; wherein said input circuit includes at least one parallel conversion circuit for converting said signals having said plurality of continuous cycles into parallel signals after retrieving said input signals; and wherein said inter-signal timing adjusting circuit adjust the outputs of said at least one parallel conversion circuit into the same phase.
Claim 69
Dependent Claim
22 words
A semiconductor device according to claim 66, wherein said plurality of said input signals are applied during one cycle of said clock.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-21 | 2003-08-23 | 2004-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-21 | 2007-08-23 | 2008-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-21 | 2011-08-23 | 2012-02-22 | $7700.00 | Window Closed / Lapsed |