Multi-bank synchronous memory system with cascade-type memory cell structure

Claim 2

A synchronous memory system with a cascade-type memory cell structure in which receiving of an address for a memory cell to be accessed and readout of data stored from the memory cell is performed in synchronization with a first clock signal supplied from an external device, the synchronous memory system comprising: a plurality of word lines; a plurality of bit lines; a plurality of first memory cells having a cascade-type configuration connected to the plurality of word lines, the plurality of first memory cells forming a first memory cell group in a plurality of first memory cell group in a memory cell array, the first memory cell group being connected to one of the plurality of bit lines; a sense amplifier for sensing data to be written into the plurality of first memory cells or for sensing data read out from the plurality of first memory cells; a plurality of second memory cells corresponding to the plurality of first memory cells; a decoder for receiving an address signal for a target memory cell to be accessed in the plurality of first memory cells in order to perform a sense operation based on the first clock signal, and controlling a transmission of data stored in each of the plurality of first memory cells into each of the plurality of second memory cells in synchronism with a second clock signal generated by using the first clock signal; and a selector for generating a control signal to select each of the plurality of first memory cells including the target memory cell based on the address signal designating the target memory cell, transmitting the control signal to the decoder, and generating a stop signal in order to halt the sense operation for the plurality of first memory cells when the transmission of data stored in the target memory cell to the sense amplifier is completed, and transmitting the stop signal to the decoder and external devices.

Claim 3

A synchronous memory system with a cascade-type memory cell structure in which receiving of an address for a memory cell to be accessed and readout of data stored from the memory cell is performed in synchronization with a first clock signal supplied from an external device, the synchronous memory system comprising: a plurality of word lines; a plurality of bit lines; a plurality of first memory cells having a cascade-type configuration connected to the plurality of word lines, the plurality of first memory cells forming a first memory cell group in a plurality of first memory cell group in a memory cell array, the first memory cell group being connected to one of the plurality of bit lines; a sense amplifier for sensing data to be written into the plurality of first memory cells or for sensing data read out from the plurality of first memory cells; a plurality of second memory cells corresponding to the plurality of first memory cells; a decoder for receiving an address signal for a target memory cell to be accessed in the plurality of first memory cells in order to perform a sense operation based on the first clock signal, and controlling a transmission of data stored in each of the plurality of first memory cells into each of the plurality of second memory cells in synchronism with a second clock signal generated by using the first clock signal; and wherein the sense amplifier comprises a first type MOS transistor pair connected in series and a second type MOS transistor pair connected in series, the first type MOS transistor pair and the second type MOS transistor pair are connected to a bit line pair in parallel, the bit line pair having first and second bit lines, gates of two of the transistors of opposite type being connected to the first bit line and gates of the other two transistors of opposite type being connected to the second bit line.

Claim 4

A synchronous memory system with a cascade-type memory cell structure in which receiving of an address for a memory cell to be accessed and readout of data stored from the memory cell is performed in synchronization with a first clock signal supplied from an external device, the synchronous memory system comprising: a plurality of word lines; a plurality of bit lines; a plurality of first memory cells having a cascade-type configuration connected to the plurality of word lines, the plurality of first memory cells forming a first memory cell group in a plurality of first memory cell group in a memory cell array, the first memory cell group being connected to one of the plurality of bit lines; a sense amplifier for sensing data to be written into the plurality of first memory cells or for sensing data read out from the plurality of first memory cells; a plurality of second memory cells corresponding to the plurality of first memory cells; a decoder for receiving an address signal for a target memory cell to be accessed in the plurality of first memory cells in order to perform a sense operation based on the first clock signal, and controlling a transmission of data stored in each of the plurality of first memory cells into each of the plurality of second memory cells in synchronism with a second clock signal generated by using the first clock signal; and wherein the sense amplifier comprises a first type MOS transistor pair connected in series and a second type MOS transistor pair connected in series, the first type MOS transistor pair and the second type MOS transistor pair are connected to a bit line pair in parallel, the bit line pair having first and second bit lines, gates of two of the transistors of opposite type being connected to the first bit line and gates of the other two transistors of opposite type being connected to the second bit line.

Claim 5

A synchronous memory system with a cascade-type memory cell structure in which receiving of an address for a memory cell to be accessed and readout of data stored from the memory cell is performed in synchronization with a first clock signal supplied from an external device, the synchronous memory system comprising: a plurality of word lines; a plurality of bit lines; a plurality of first memory cells having a cascade-type configuration connected to the plurality of word lines, the plurality of first memory cells forming a first memory cell group in a plurality of first memory cell group in a memory cell array, the first memory cell group being connected to one of the plurality of bit lines; a sense amplifier for sensing data to be written into the plurality of first memory cells or for sensing data read out from the plurality of first memory cells; a plurality of second memory cells corresponding to the plurality of first memory cells; a decoder for receiving an address signal for a target memory cell to be accessed in the plurality of first memory cells in order to perform a sense operation based on the first clock signal, and controlling a transmission of data stored in each of the plurality of first memory cells in to each of the plurality of second memory cells in synchronism with a second clock signal generated by using the first clock signal; and wherein the number of the plurality of first memory cells connected in the cascade-type configuration per first memory cell group is four first memory cells.

Claim 6

A synchronous memory system with a cascade-type memory cell structure in which receiving of an address for a memory cell to be accessed and readout of data stored from the memory cell is performed in synchronization with a first clock signal supplied from an external device, the synchronous memory system comprising: a plurality of word lines; a plurality of bit lines; a plurality of first memory cells having a cascade-type configuration connected to the plurality of word lines, the plurality of first memory cells forming a first memory cell group in a plurality of first memory cell group in a memory cell array, the first memory cell group being connected to one of the plurality of bit lines; a sense amplifier for sensing data to be written into the plurality of first memory cells or for sensing data read out from the plurality of first memory cells; a plurality of second memory cells corresponding to the plurality of first memory cells; a decoder for receiving an address signal for a target memory cell to be accessed in the plurality of first memory cells in order to perform a sense operation based on the first clock signal, and controlling a transmission of data stored in each of the plurality of first memory cells in to each of the plurality of second memory cells in synchronism with a second clock signal generated by using the first clock signal; and wherein the number of the plurality of first memory cells connected in the cascade-type configuration per first memory cell group is four first memory cells.

Claim 7

A synchronous memory system with a cascade-type memory cells as claimed in claim 3, wherein the plurality of second memory cells comprises first to fourth cells, each cell comprises a capacitor and a MOS transistor, a source of the MOS transistor in the first cell is connected to a source of the MOS transistor in the second cell, a source of the MOS transistor in the third cell is connected to a source of the MOS transistor in the fourth cell, each source of the MOS transistor in the first to fourth cells is connected to each of the plurality of bit lines, each drain of the MOS transistor is connected to the capacitor in each of the first to fourth cells.

Claim 8

A synchronous memory system with a cascade-type memory cells as claimed in claim 3, wherein the plurality of second memory cells comprises first to third cells, each cell comprises a capacitor and a MOS transistor, a source of the MOS transistor in the first cell is connected to a source of the MOS transistor in the second cell, each source of the MOS transistor in the first to third cells is connected to each of the plurality of bit lines, each drain of the MOS transistor is connected to the capacitor in each of the first to third cells.

Claim 9

A synchronous memory system with a cascade-type memory cells as claimed in claim 3, wherein the plurality of second memory cells comprises first to fourth cells, each of the first to fourth cells comprises a first MOS transistor and a second MOS transistor connected in series, an intermediate point of the first MOS transistor and the second MOS transistor is connected to a flip/flop circuit (F/F), gates of the first MOS transistor and the second MOS transistor are connected to each of the plurality of bit lines.

Claim 10

A synchronous memory system with a cascade-type memory cells as claimed in claim 3, wherein the plurality of second memory cells comprises four first memory cells connected to each other in the cascade-type structure, and one of the plurality of second memory cells located at a first end position is connected to one of the plurality of bit lines, and data items stored in the four first memory cells are saved into the second memory cells, a save operation is initialed from a second memory cell located at the opposite end position to the first end position in the second memory cells.

Claim 11

A synchronous memory system with a cascade-type memory cells as claimed in claim 3, wherein the plurality of second memory cells comprises three first memory cells connected to each other in the cascade-type structure, and one of the plurality of second memory cells located at a first end position is connected to one of the plurality of bit lines, data items stored in the first memory cells are saved into the second memory cells, and a save operation is initiated from a second memory cell located at the opposite end position to the first end position in the second memory cells.

Claim 12

A synchronous memory system with a cascade-type memory cells as claimed in claim 3, wherein the plurality of second memory cells comprises four first memory cells connected to each other in the cascade-type structure, and both ends of the plurality of first memory cells are connected to one of the plurality of bit lines, both ends of the plurality of second memory cells are connected to the bit line, and data items stored in the plurality of first memory cells are saved into the plurality of second memory cells cyclicly.

Claim 13

A synchronous memory system with a cascade-type memory cells as claimed in claim 3, wherein the plurality of second memory cells comprises three cells each of which comprises a MOS transistor and a flip/flop circuit (F/F), a source of the MOS transistor is connected to each of the plurality of bit lines, and a drain of the MOS transistor is connected to the flip/flop.

Claim 14

A multi-bank synchronous memory system with a multi-bank structure comprising: a plurality of synchronous memory systems with a cascade-type memory cell structure in which receiving of an address for a memory cell to be accessed and readout of data stored from the memory cell being performed in synchronization with a first clock signal supplied externally, and the plurality of synchronous memory cell systems being divided into a plurality of banks in a multi-bank structure, data in the memory cell in each bank being sensed independently, and each of the plurality of synchronous memory systems comprising: a plurality of word lines; a plurality of bit lines; a plurality of first memory cells having a cascade-type configuration connected to the plurality of word selection lines, the plurality of first memory cells forming a memory cell group in a plurality of memory cell groups in a memory cell array, the memory cell group being connected to one of the plurality of bit lines; a plurality of transfer gates provided to each of the plurality of the bit lines to connect each memory cell group to each of the plurality of the bit lines; a sense amplifier connected to each of the plurality of bit lines for storing data to be written into each of the plurality of first memory cells or for storing data to be read out from each of the plurality of first memory cells; an equalizer provided for the sense amplifier for equalizing a voltage potential of each of the plurality of bit lines; a plurality of second memory cells located between the plurality of first memory cells and the sense amplifier, the plurality of second memory cells provided for the plurality of first memory cells; a selector for receiving an address of a target memory cell to be accessed in the plurality of first memory cells according to the first clock signal, selecting each of the plurality of first memory cells while saving data of the selected each of the plurality of first memory cells to the plurality of second memory cells in synchronism with the first clock signal and counting a number of the selected each of the plurality of first memory cells, generating a sense operation halt control signal when the target memory cell being selected and whose data being stored to the sense amplifier, and transmitting the sense operation halt control signal externally; and a decoder for receiving the address of the target memory cell and generates access control signals for controlling operations of the plurality of first memory cells, the plurality of transfer gates, the sense amplifier, the equalizer, and the plurality of second memory cells, and transmits the address control signals to the plurality of word lines, the plurality of transfer gates, the plurality of second memory cells, and the sense amplifier, wherein when a memory cell in the plurality of first memory cells in another memory cell group connected is a target memory cell to be accessed in series, a sense operation for the first memory cells including the target memory cell in another memory cell group is executed after the data items temporarily have been saved into the plurality of second memory cells are restored into corresponding the plurality of first memory cells including the preceding target memory cell.

Claim 15

A multi-bank synchronous memory system with a multi-bank structure comprising: a plurality of synchronous memory systems with a cascade-type memory cell structure in which receiving of an address for a memory cell to be accessed and readout of data stored from the memory cell being performed in synchronization with a first clock signal supplied externally, and the plurality of synchronous memory cell systems being divided into a plurality of banks in a multi-bank structure, data in the memory cell in each bank being sensed independently, and each of the plurality of synchronous memory systems comprising: a plurality of word lines; a plurality of bit lines; a plurality of first memory cells having a cascade-type configuration connected to the plurality of word selection lines, the plurality of first memory cells forming a memory cell group in a plurality of memory cell groups in a memory cell array, the memory cell group being connected to one of the plurality of bit lines; a plurality of transfer gates provided to each of the plurality of the bit lines to connect each memory cell group to each of the plurality of the bit lines; a sense amplifier connected to each of the plurality of bit lines for storing data to be written into each of the plurality of first memory cells or for storing data to be read out from each of the plurality of first memory cells; an equalizer provided for the sense amplifier for equalizing a voltage potential of each of the plurality of bit lines; a plurality of second memory cells located between the plurality of first memory cells and the sense amplifier, the plurality of second memory cells provided for the plurality of first memory cells; a selector for receiving an address of a target memory cell to be accessed in the plurality of first memory cells according to the first clock signal, selecting each of the plurality of first memory cells while saving data of the selected each of the plurality of first memory cells to the plurality of second memory cells in synchronism with the first clock signal and counting a number of the selected each of the plurality of first memory cells, generating a sense operation halt control signal when the target memory cell being selected and whose data being stored to the sense amplifier, and transmitting the sense operation halt control signal externally; and a decoder for receiving the address of the target memory cell and generates access control signals for controlling operations of the plurality of first memory cells, the plurality of transfer gates, the sense amplifier, the equalizer, and the plurality of second memory cells, and transmits the address control signals to the plurality of word lines, the plurality of transfer gates, the plurality of second memory cells, and the sense amplifier, wherein when a memory cell in the plurality of first memory cells in another memory cell group connected is a target memory cell to be accessed in series, a sense operation for the first memory cells including the target memory cell in another memory cell group is executed after the data items temporarily have been saved into the plurality of second memory cells are restored into corresponding the plurality of first memory cells including the preceding target memory cell.

Claim 16

A multi-bank synchronous memory system as claimed in claim 11, wherein the memory cell in the cascade-type structure in one bank are selected for data access operation and this data is stored in the sense amplifier during an output operation for data of a memory cell in another bank, and when a request for a data transfer of the memory cell in this another bank is happened, the data in the memory cell in the one bank is not stored into the sense amplifier, or not have been completed, a signal indicating that the data access operation is not possible is transmitted externally.

Claim 17

A multi-bank synchronous memory system as claimed in claim 11, wherein the plurality of memory cell groups in each bank are further divided into at least two memory cell groups in which data of the plurality of memory cells in a cascade-type structure in each bank group can be sensed and stored into each of the sense amplifier respectively and independently, data transfer operation for one bank group is continuously performed after this one bank group has been activated, and other bank group is activated while this one bank group is accessed for the data transfer, and the data transfer operation of the one bank group and the data transfer operation of the other bank group are executed in a combined cycle, and the data transfer operations of the plurality of bank groups are divided into a group of congestion cycles to be executed correctly.

Claim 18

A multi-bank synchronous memory system with a cascade-type memory cell structure comprising a plurality of memory chips, each memory chip comprising a synchronous memory system as claimed in claim 11, the plurality of memory chips being arranged in matrix, and the plurality of memory chips being divided into at least two bank groups, wherein data transfer operation for one bank group is continuously performed after this one bank group has been activated, and other bank group is activated while this one bank group is accessed for the data transfer, and the data transfer operation for the one bank group and the data transfer operation for the other bank group are executed in a combined cycle, and the data transfer operations of the plurality of bank groups are divided into a group of congestion cycles to be executed correctly.