US5287312A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory
Assignee: Toshiba Corp
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Filing: 1991-12-26
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Granted: 1994-02-15
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Expires: 2011-12-26
Abstract
Abstract A dynamic random access memory according to the present invention comprises a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.
Inventors
- 👤 Junichi Okamura
- 👤 Tohru Furuyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085; G11C11/4087; G11C29/00; G11C29/04; G11C29/50; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
418 words
A semiconductor memory device, comprising: dynamic memory cells arranged in a row and column array, each of said dynamic memory cells comprising a transfer MOS transistor of a first conductivity type and a capacitive element coupled to said transfer MOS transistor for storing data; word lines each connecting the dynamic memory cells in one row of said array; bit lines each connecting the dynamic memory cells in one column of said array; pads for receiving external address signals; address amplifying circuits coupled to said pads and responsive to the external address signals for generating first internal address signals for selecting a first number of said word lines in a normal operation mode; a control circuit responsive to a voltage stress test control signal for generating second internal address signals for selecting a second number of said word lines in a voltage stress test mode, the second number being greater than the first number; word line selecting circuits responsive to the first and second internal address signals for outputting word line selecting signals to select ones of said word lines; a word line driving voltage source for outputting a word line driving voltage; and word line driving circuits each coupled between corresponding ones of said word lines and said word line selecting circuits and responsive to said word line selecting signals for driving selected word lines, each of said word line driving circuits including: a first transistor of the first conductivity type having a first current terminal coupled to the corresponding one of said word line selecting circuits, a second current terminal, and a control terminal coupled to a power supply potential; a second transistor of a second conductivity type opposite the first conductivity type having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to the corresponding one of said word lines, and a control terminal coupled to said second current terminal of said first transistor; a third transistor of the first conductivity type having a first current terminal coupled to the corresponding ones of said word lines, a second current terminal coupled to a ground potential, and a control terminal coupled to the corresponding one of said word line selecting circuits; and a fourth transistor of the second conductivity type having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to said control terminal of said second transistor, and a control terminal coupled to the corresponding one of said word lines.
Claim 2
Dependent Claim
418 words
A semiconductor memory device, comprising: dynamic memory cells arranged in a row and column array, each of said dynamic memory cells comprising a transfer MOS transistor of a first conductivity type and a capacitive element coupled to said transfer MOS transistor for storing data; word lines each connecting the dynamic memory cells in one row of said array; bit lines each connecting the dynamic memory cells in one column of said array; pads for receiving external address signals; address amplifying circuits coupled to said pads and responsive to the external address signals for generating first internal address signals for selecting a first number of said word lines in a normal operation mode; a control circuit responsive to a voltage stress test control signal for generating second internal address signals for selecting a second number of said word lines in a voltage stress test mode, the second number being greater than the first number; word line selecting circuits responsive to the first and second internal address signals for outputting word line selecting signals to select ones of said word lines; a word line driving voltage source for outputting a word line driving voltage; and word line driving circuits each coupled between corresponding ones of said word lines and said word line selecting circuits and responsive to said word line selecting signals for driving selected word lines, each of said word line driving circuits including: a first transistor of the first conductivity type having a first current terminal coupled to the corresponding one of said word line selecting circuits, a second current terminal, and a control terminal coupled to a power supply potential; a second transistor of a second conductivity type opposite the first conductivity type having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to the corresponding one of said word lines, and a control terminal coupled to said second current terminal of said first transistor; a third transistor of the first conductivity type having a first current terminal coupled to the corresponding ones of said word lines, a second current terminal coupled to a ground potential, and a control terminal coupled to the corresponding one of said word line selecting circuits; and a fourth transistor of the second conductivity type having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to said control terminal of said second transistor, and a control terminal coupled to the corresponding one of said word lines.
Claim 3
Dependent Claim
335 words
The semiconductor memory device, according to claim 1, wherein said word line driving voltage source comprises: a word line driving voltage source output terminal for outputting the word line driving voltage; a clock signal generating circuit having first and second outputs; an inverter having a first terminal coupled to said first output of said clock signal generating circuit, and a second terminal; a first capacitor having a first terminal coupled to said second terminal of said inverter, and a second terminal; a second capacitor having a first terminal coupled to said second output of said clock signal generating circuit, and a second terminal; a fifth MOS transistor having a first current terminal coupled to said second terminal of said first capacitor, a second current terminal coupled to receive the power supply voltage, and a control terminal coupled to said second output of said clock signal generating circuit; a sixth MOS transistor having a first current terminal coupled to said second terminal of said first capacitor, a second current terminal coupled to receive the power supply voltage, and a control terminal coupled to said second terminal of said inverter; a seventh MOS transistor having a first current terminal coupled to a connection node between said second terminal of said first capacitor and said first current terminal of said fifth MOS transistor, a second current terminal coupled to said word line driving voltage source output terminal, and a control terminal coupled to said connection node between said second terminal of said first capacitor and said first current terminal of said fifth MOS transistor; and a eighth MOS transistor having a first current terminal coupled to a connection node between said second terminal of said second capacitor and said first current terminal of said sixth MOS transistor, a second current terminal coupled to said word line driving voltage source output terminal, and a control terminal coupled to said connection node between said second terminal of said first capacitor and said first current terminal of said sixth MOS transistor.
Claim 4
Dependent Claim
126 words
The semiconductor memory device according to claim 1, further comprising: a bit line voltage application circuit, said bit line voltage application circuit including a bit line voltage application circuit output terminal, a voltage generating circuit for generating a first voltage, a terminal coupled to the ground voltage, and a switch for selectively coupling said bit line voltage application circuit output terminal to one of the first voltage and the ground voltage; switching transistors each having a first current terminal coupled to a corresponding one of said bit lines, a second current terminal coupled to said bit line application circuit output terminal, and a control terminal coupled to receive a switching signal for selectively coupling said bit lines to said bit line voltage application circuit output terminal.
Claim 5
Dependent Claim
98 words
The semiconductor memory device according to claim 1, further comprising: a pad for receiving an externally supplied word line driving voltage during the voltage stress test mode; a switching circuit having a first input terminal coupled to said word line driving voltage source, a second input terminal coupled to said pad, and an output terminal coupled to said first current terminal of said second transistor, said switching circuit supplying a voltage output by said word line driving voltage source during the normal operation mode and supplying a voltage received at said pad during the voltage stress test mode.
Claim 6
Dependent Claim
388 words
A semiconductor memory device, comprising: dynamic memory cells arranged in a row and column array, each of said dynamic memory cells comprising a transfer MOS transistor of a first conductivity type and a capacitive element coupled to said transfer MOS transistor for storing data; word lines each connecting the dynamic memory cells in one row of said array; bit lines each connecting the dynamic memory cells in one column of said array; pads for receiving external address signals; address amplifying circuits coupled to said pads and responsive to the external address signals for generating first internal address signals for selecting a first number of said word lines in a normal operation mode; a word line driving voltage source; word line selecting circuits responsive to the first internal address signals for outputting word line selecting signals to select ones of said word lines, said word line selecting circuits each comprising a logic gate for decoding the first internal address signals and a precharge transistor having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to an output of said logic gate, and a control terminal receiving a precharge signal for precharging said output of said logic gate; a control circuit responsive to a voltage stress test control signal for selecting a second number of said word lines in a voltage stress test operation mode, the second number being greater than the first arbitrary number; and word line driving circuits coupled between corresponding ones of said word line selecting circuits and said word lines, and responsive to the word line selecting signals and said control circuit for driving selected word lines, said word line driving circuits comprising a CMOS inverter including a first transistor of a second conductivity type opposite the first conductivity type having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to the corresponding one of said word lines, and a control terminal connected to the corresponding one of said word line selecting circuits, and a second transistor of the first conductivity type having a first current terminal coupled to the corresponding one of said word lines, a second current terminal coupled to the ground potential, and a control terminal coupled to the corresponding one of said word line selecting circuits.
Claim 7
Dependent Claim
388 words
A semiconductor memory device, comprising: dynamic memory cells arranged in a row and column array, each of said dynamic memory cells comprising a transfer MOS transistor of a first conductivity type and a capacitive element coupled to said transfer MOS transistor for storing data; word lines each connecting the dynamic memory cells in one row of said array; bit lines each connecting the dynamic memory cells in one column of said array; pads for receiving external address signals; address amplifying circuits coupled to said pads and responsive to the external address signals for generating first internal address signals for selecting a first number of said word lines in a normal operation mode; a word line driving voltage source; word line selecting circuits responsive to the first internal address signals for outputting word line selecting signals to select ones of said word lines, said word line selecting circuits each comprising a logic gate for decoding the first internal address signals and a precharge transistor having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to an output of said logic gate, and a control terminal receiving a precharge signal for precharging said output of said logic gate; a control circuit responsive to a voltage stress test control signal for selecting a second number of said word lines in a voltage stress test operation mode, the second number being greater than the first arbitrary number; and word line driving circuits coupled between corresponding ones of said word line selecting circuits and said word lines, and responsive to the word line selecting signals and said control circuit for driving selected word lines, said word line driving circuits comprising a CMOS inverter including a first transistor of a second conductivity type opposite the first conductivity type having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to the corresponding one of said word lines, and a control terminal connected to the corresponding one of said word line selecting circuits, and a second transistor of the first conductivity type having a first current terminal coupled to the corresponding one of said word lines, a second current terminal coupled to the ground potential, and a control terminal coupled to the corresponding one of said word line selecting circuits.
Claim 8
Dependent Claim
71 words
The semiconductor memory device according to claim 5, wherein said control circuit comprises circuitry connected between said address amplifiers and said word line selecting circuits for supplying the first internal address signals to said word line selecting circuits in the normal operation mode and for supplying second internal address signals for selecting the second number of word lines to said word line selecting circuits in the voltage stress test operation mode.
Claim 9
Dependent Claim
53 words
The semiconductor memory device according to claim 5, wherein said control circuit comprises: MOS transistors each having a first current terminal coupled to the output of a corresponding one of said logic gates, a second current terminal coupled to the ground potential, and a control terminal receiving the voltage stress test control signal.
Claim 10
Dependent Claim
98 words
The semiconductor memory device according to claim 5, further comprising: a pad for receiving an externally supplied word line driving voltage during the voltage stress test mode; a switching circuit having a first input terminal coupled to said word line driving voltage source, a second input terminal coupled to said pad, and an output terminal coupled to said first current terminal of said second transistor, said switching circuit supplying a voltage output by said word line driving voltage source during the normal operation mode and supplying a voltage received at said pad during the voltage stress test mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |