Semiconductor memory device having a word driver

Claim 2

A semiconductor memory device, comprising: a word line; selecting means for generating a selecting signal for selecting said word line; driving means for driving said word line in response to said selecting signal; said driving means including a transfer transistor having a gate receiving a power supply voltage and for transmitting a voltage responding to said selecting signal, and a driver transistor having a gate receiving a voltage transmitted by said transfer transistor and for charging said word line to a predetermined voltage, and boosting means for boosting a voltage to be applied to the gate of said transfer transistor to a voltage of said power supply voltage plus a predetermined voltage lower than a threshold voltage of said transfer transistor.

Claim 3

The semiconductor memory device according to claim 1, wherein said driving means further comprises a first node receiving a driving signal having a voltage higher than the power supply voltage, a second node receiving said voltage responding to said selecting signals, and discharging means responsive to said selecting signal for discharging said word line, said driver transistor is connected between said first node and said word line, and said transfer transistor is connected between said second node and the gate of said driver transistor.

Claim 4

The semiconductor memory device according to claim 1, further comprising clamping means for clamping said boosted voltage to a constant voltage.

Claim 5

The semiconductor memory device according to claim 1, further comprising receiving means receiving a control signal for defining an active period wherein said boosting means boosts a voltage to be applied to the gate of said transfer transistor in response to said control signal.

Claim 6

A semiconductor memory device, comprising: a word line; selecting means for generating a selecting signal for selecting said word line; driving means for driving said word line in response to said selecting signal, said driving means including; a transfer transistor having a gate receiving a power supply voltage and for transmitting a voltage responding to said selecting signal, and a driver transistor having a gate receiving a voltage transmitted by said transfer transistor and for charging said word line to a predetermined voltage, and voltage control means responsive to initiation of an active period for boosting a voltage to be applied to the gate of said transfer transistor to a voltage of said power supply voltage plus a threshold voltage of said transfer transistor, and responsive to drive of said word line for pulling down said boosted voltage to said power supply voltage.

Claim 7

A semiconductor memory device, comprising: a word line; selecting means for generating a selecting signal for selecting said word line; driving means for driving said word line in response to said selecting signal, said driving means including; a transfer transistor having a gate receiving a power supply voltage and for transmitting a voltage responding to said selecting signal, and a driver transistor having a gate receiving a voltage transmitted by said transfer transistor and for charging said word line to a predetermined voltage, and voltage control means responsive to initiation of an active period for boosting a voltage to be applied to the gate of said transfer transistor to a voltage of said power supply voltage plus a threshold voltage of said transfer transistor, and responsive to drive of said word line for pulling down said boosted voltage to said power supply voltage.

Claim 8

The semiconductor memory device according to claim 5, wherein said driving means further comprises a first node receiving a driving signal having a voltage higher than a power supply voltage, a second node receiving said voltage responding to said selecting signal, and discharging means responsive to said selecting signal for discharging said word line, said driver transistor is connected between said first node and said word line, and said transfer transistor is connected between said second node and the gate of said driver transistor.

Claim 9

The semiconductor memory device according to claim 5, further comprising clamping means for clamping said boosted voltage to a constant voltage.

Claim 10

The semiconductor memory device according to claim 5, further comprising receiving means receiving a control signal for defining an active period, wherein said voltage control means boosts a voltage to be applied to gate of said transfer transistor in response to said control signal, and pulls down said boosted voltage to said power supply voltage in response to a delay signal of said control signal.

Claim 11

A semiconductor memory device, comprising: a word line; selecting means for generating a selecting signal for selecting said word line; driving means responsive to said selecting signal for driving said word line; and high voltage generating means for generating a predetermined high voltage higher than a power supply voltage, said driving means including high voltage supplying means responsive to said selecting signal for supplying said high voltage, a transfer transistor having a gate receiving said high voltage from said high voltage generating means and for transmitting a voltage from said high voltage supplying means, and a driver transistor having a gate receiving a voltage transmitted by said transfer transistor and for charging said word line to a predetermined voltage.

Claim 12

A semiconductor memory device, comprising: a word line; selecting means for generating a selecting signal for selecting said word line; driving means responsive to said selecting signal for driving said word line; and high voltage generating means for generating a predetermined high voltage higher than a power supply voltage, said driving means including high voltage supplying means responsive to said selecting signal for supplying said high voltage, a transfer transistor having a gate receiving said high voltage from said high voltage generating means and for transmitting a voltage from said high voltage supplying means, and a driver transistor having a gate receiving a voltage transmitted by said transfer transistor and for charging said word line to a predetermined voltage.

Claim 13

The semiconductor memory device according to claim 9, wherein said high voltage supplying means comprise a first node receiving a voltage responding to said selecting signal, a second node connected to said transfer transistor, first charging means responsive to a voltage of said second node for charging said first node to said high voltage at the time of non-selection, and second charging means responsive to a voltage of said first node for charging said second node to said high voltage at the time of selection.

Claim 14

The semiconductor memory device according to claim 10, wherein said high voltage supplying means further comprises first discharging means for discharging said first node at the time of selection, and second discharging means for discharging said second node at the time of non-selection.

Claim 15

The semiconductor memory device according to claim 10, wherein said driving means further comprises a transfer transistor having a gate receiving said power supply voltage and connected between an output of said selecting means and said first node.

Claim 16

The semiconductor memory device according to claim 12, wherein said high voltage supplying means further comprises discharging means for discharging said second node at the time of non-selection.

Claim 17

The semiconductor memory device according to claim 11, wherein said driving means further comprises a third node receiving a driving signal having a voltage higher than a power supply voltage, and third discharging means responsive to said selecting signal for discharging said word line, said driver transistor is connected between said third node and said word line, and said transfer transistor is connected between said second node and the gate of said driver transistor.

Claim 18

The semiconductor memory device according to claim 13, wherein said driving means further comprises a third node receiving a driving signal having a voltage higher than said power supply voltage, and second discharging means responsive to said selecting signal for discharging said word line, said driver transistor is connected between said third node and said word line, and said transfer transistor is connected between said second node and the gate of said driver transistor.

Claim 19

A semiconductor memory device, comprising: a plurality of word lines; a plurality of driving means provided corresponding to said plurality of word lines; selecting means provided in common to said plurality of driving means for generating a selecting signal; and switching means connected between said selecting means and said plurality of driving means for selectively transmitting the selecting signal from said selecting means to any of said plurality of driving means, each of said plurality of driving means including a transfer transistor for transmitting a voltage responding to said selecting signal, a driver transistor having a gate receiving a voltage transmitted by said transfer transistor and for charging a corresponding word line to a predetermined voltage, and voltage supplying means for supplying a predetermined voltage higher than a power supply voltage to the gate of said transfer transistor.

Claim 20

A semiconductor memory device, comprising: a plurality of word lines; a plurality of driving means provided corresponding to said plurality of word lines; selecting means provided in common to said plurality of driving means for generating a selecting signal; and switching means connected between said selecting means and said plurality of driving means for selectively transmitting the selecting signal from said selecting means to any of said plurality of driving means, each of said plurality of driving means including a transfer transistor for transmitting a voltage responding to said selecting signal, a driver transistor having a gate receiving a voltage transmitted by said transfer transistor and for charging a corresponding word line to a predetermined voltage, and voltage supplying means for supplying a predetermined voltage higher than a power supply voltage to the gate of said transfer transistor.

Claim 21

The semiconductor memory device according to claim 16, further comprising high voltage generating means for generating a predetermined high voltage higher than said power supply voltage; wherein said switching means includes a plurality of switch transistors respectively connected between said selecting means and said plurality of driving means; each of said plurality of driving means further includes: high voltage supplying means responsive to said selecting signal for supplying said high voltage to said transfer transistor as said voltage responding to said selecting signal; said high voltage supplying means includes a first node connected to a corresponding switch transistor, a second node connected to said transfer transistor, first charging means responsive to a voltage of said second node for charging said first node to said high voltage at the time of non-selection, second charging means responsive to a voltage of said first node for charging said second node to said high voltage at the time of selection, and first discharging means responsive to a predetermined reset signal for discharging said second node at the time of non-selection.

Claim 22

The semiconductor memory device according to claim 17, wherein said high voltage supplying means further comprises second discharging means responsive to a voltage of said first node for discharging said second node.

Claim 23

The semiconductor memory device according to claim 17, wherein said driving means further comprises a third node receiving a driving signal having a voltage higher than a power supply voltage, and second discharging means responsive to said selecting signal for discharging said word line, said driver transistor is connected between said third node and said corresponding word line, and said transfer transistor is connected between said second node and the gate of said driver transistor.

Claim 24

The semiconductor memory device according to claim 18, wherein each of said driving means further comprises a third node receiving a driving signal having a voltage higher than a power supply voltage, and third discharging means responsive to said selecting signal for discharging a corresponding word line, said driver transistor is connected between said third node and said word line, and said transfer transistor is connected between said second node and the gate of said driver transistor.