Digital phase alignment and integrated multichannel transceiver employing same

Claim 2

The synchronizer of claim 1, wherein said clock adjustment means includes means for initially producing the sampling clock signal to be synchronous with the reference clock signal and for subsequently adjusting the phase of the sampling clock signal relative to the input signal when the reference clock signal is substantially in phase with the input signal such that the clocking transition of the sampling clock signal is phase offset from the data transition of the input signal.

Claim 3

The synchronizer of claim 1, wherein the synchronous replica comprises an input replica most closely synchronized with the sampling clock signal.

Claim 4

The synchronizer of claim 1, wherein the synchronous replica comprises a one of said input replicas having a phase which leads the sampling clock signal.

Claim 5

The synchronizer of claim 1, wherein said output means further includes compensation means for evaluating the synchronous replica for cycle slip, and wherein when found, the data output signal comprises a slip-cycle compensated data output signal, said slip-cycle compensated data output signal being closely synchronized with the reference clock signal, and wherein said selection means includes means for storing a previous synchronous replica, and wherein said compensation means includes means for comparing the phase of the synchronous replica with a phase of the previous synchronous replica and wherein said cycle slip evaluation includes means for examining the synchronous replica and the previous synchronous replica for a predefined phase difference, and wherein said compensation means includes means for deleting the data output signal when the phase of the synchronous replica lags by more than 360° the phase of the previous synchronous replica, and wherein said compensation means includes means for adding an output data bit before outputting of the synchronous replica as the data output signal when the phase of the synchronous replica leads the phase of the previous synchronous replica by more than 360°.

Claim 6

The synchronizer of claim 1, further comprising an elastic buffer and byte synchronizer, coupled to the output means, for receiving the data output signal for byte synchronizing.

Claim 7

The synchronizer of claim 1, wherein said selection means includes a multiplexer circuit for selection of the synchronous replica from the input replicas output by the delay circuit.

Claim 8

A synchronizer for phase aligning an input signal with a reference clock signal, said synchronizer comprising: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; means for acquiring phase states for each input replica relative to the reference clock signal, including means for evaluating the acquired phase states, beginning with a phase state corresponding with a least delayed input replica, for detecting a first phase state transition and when detected, for setting each acquired phase state subsequent thereto to a predefined, set phase state; selection means, coupled to said means for acquiring phase states, for identifying based on phase states one of the input replicas as closely synchronized with the reference clock signal, said identified one of the input replicas comprising a synchronous replica; and means for outputting the synchronous replica as a data output signal synchronized with the reference clock signal.

Claim 9

The synchronizer of claim 8, wherein said delay circuit, said phase state acquiring means, said selection means and said outputting means are each digitally implemented.

Claim 10

The synchronizer of claim 8, wherein the synchronous replica identified by said selection means comprises an input replica most closely synchronized with the reference clock signal.

Claim 11

The synchronizer of claim 8, wherein the synchronous replica identified by said selection means comprises a one of said input replicas having a phase which leads the reference clock signal, wherein said means for outputting includes compensation means for evaluating the synchronous replica for cycle slip, and when identified, for outputting the data output signal as a slip-cycle compensated data output signal synchronized with the reference clock signal, wherein said selection means includes means for saving a previous synchronous replica, and said compensation means includes means for comparing the phase of the synchronous replica with a phase of the previous synchronous replica, said means for evaluating cycle slip including means for identifying a phase difference between the phase of the synchronous replica and the phase of the previous synchronous replica, wherein said compensation means includes means for deleting the data output signal when the phase of the synchronous replica lags by more that 360° the phase of the previous synchronous replica, and wherein said compensation means includes means for adding an output data bit before the data output signal when the phase of the synchronous replica leads the phase of the previous synchronous replica by more than 360°, and wherein said selection means includes means for determining a phase change direction between the synchronous replica and the previous synchronous replica and for providing based thereon a corresponding lead/lag signal to said outputting means.

Claim 12

The synchronizer of claim 8, further comprising clock adjustment means for receiving the reference clock signal and for producing therefrom a sampling clock signal having a clocking transition, said sampling clock signal having a same frequency as the reference clock signal and a phase offset from the input signal, the phase of the sampling clock signal being offset from the reference clock signal when the reference clock signal is substantially in phase with the input signal; and wherein: said selection means includes means for detecting a phase relationship between the sampling clock signal and at least some of the input replicas, and for identifying based thereon one of said input replicas is closely synchronized with the sampling clock signal, said identified one of the input replicas comprising a synchronous replica; said means for outputting includes means for retiming the synchronous replica by compensating for said clock adjustment means' sampling clock signal phase offset relative to the reference clock signal when the reference clock signal is substantially in phase with the input signal; and said clock adjustment means includes means for initially producing the sampling clock signal to be synchronous with the reference clock signal and for subsequently adjusting the phase of the sampling clock signal relative to the input signal when the reference clock signal is substantially in phase with the input signal such that the clocking transition of the sampling clock signal is phase offset from the data transition of the input signal.

Claim 13

A synchronizer for phase aligning an input signal with a reference clock signal, said synchronizer comprising: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; selection means, coupled to the delay circuit, for identifying one of said input replicas as closely synchronized with the reference clock signal, said identified one of the input replicas comprising a synchronous replica; and compensation means for evaluating the synchronous replica for cycle slip, and for outputting based thereon, a slip-cycle compensated data output signal whenever a cycle slip is determined, said slip-cycle compensated data output signal being closely synchronized with the reference clock signal.

Claim 14

The synchronizer of claim 13, wherein said synchronous replica comprises a one of said input replicas most closely synchronized with the reference clock signal.

Claim 15

The synchronizer of claim 13, wherein said synchronous replica comprises a one of said input replicas having a phase which leads the reference clock signal.

Claim 16

The synchronizer of claim 13, wherein said selection means includes means for saving a previous synchronous replica, and said compensation means includes means for comparing the phase of the synchronous replica with a phase of the previous synchronous replica, said compensation means' cycle slip evaluating being based on a phase difference between the phase of the synchronous replica and the phase of the previous synchronous replica, wherein said compensation means includes means for deleting the data output signal when the phase of the synchronous replica lags by more than 360° the phase of the previous synchronous replica, and wherein said compensation means includes means for adding an output data bit before the data output signal when the phase of the synchronous replica leads the phase of the previous synchronous replica by more than 360°, and wherein said selection means further comprises means for determining phase change direction between the synchronous replica and the previous synchronous replica, and for outputting based thereon a corresponding lead/lag signal to said compensating means for use in said cycle slip evaluation.

Claim 17

The synchronizer of claim 13, further comprising output means for outputting the synchronous replica as the data output signal synchronized with the reference clock signal when no cycle slip is determined by said compensation means.

Claim 18

A synchronizer for phase aligning an input signal, having a data transition, with a reference clock signal, said synchronizer comprising: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; clock adjustment means for receiving the reference clock signal and for producing therefrom a sampling clock signal having a clocking transition, said sampling clock signal having a same frequency as the reference clock signal and a phase offset from the input signal; means for acquiring phase states for the input replicas relative to the sampling clock signal, said means for acquiring phase states including means for filtering incorrect phase states; selection means, coupled to said means for acquiring phase states, for identifying based on acquired phase states one of the input replicas as closely synchronized with the sampling clock signal, said identified one of the input replicas comprising a synchronous replica; and retiming and cycle-slip compensation means for outputting a slip-cycle compensated data output signal closely synchronized with the reference clock signal, said retiming means including means for adjusting the phase of the synchronous replica when the sampling clock signal is phase offset from the reference clock signal, said phase compensating of the synchronous replica being equal to the phase offset of the sampling clock signal relative to the reference clock signal.

Claim 19

The synchronizer of claim 18, wherein said clock adjustment means includes means for providing the sampling clock signal synchronous with the reference clock signal when the reference clock signal is phase offset from the input signal, wherein said adjustment means includes means for initially producing the sampling clock signal to be synchronous with the reference clock signal and for subsequently adjusting the phase of the sampling clock signal relative to the input signal when the reference clock signal is substantially in phase with the input signal such that the clocking transition of the sampling clock signal is phase offset from the data transition of the input signal.

Claim 20

The synchronizer of claim 18, wherein the synchronous replica comprises an input replica most closely synchronized with the sampling clock signal.

Claim 21

The synchronizer of claim 18, wherein the synchronous replica comprises a one of said input replicas having a phase which leads the sampling clock signal.

Claim 22

The synchronizer of claim 18, wherein said selection means includes means for storing a previous synchronous replica, and wherein said compensation means includes means for comparing the phase of the synchronous replica with the phase of the previous synchronous replica and wherein said cycle slip evaluation includes means for examining the synchronous replica and the previous synchronous replica for a predefined phase difference, wherein said compensation means includes means for deleting the data output signal when the phase of the synchronous replica lags by more than 360° the phase of the previous synchronous replica, and wherein said compensation means includes means for adding an output data bit before outputting of the synchronous replica as the data output signal when the phase of the synchronous replica leads the phase of the previous synchronous replica by more than 360°, and wherein said selection means includes means for determining a phase change direction between the synchronous replica and the previous replica and for providing to said retiming and cycle slip compensation means a corresponding lead/lag signal.

Claim 23

The synchronizer of claim 18, wherein said means for acquiring phase states includes means for evaluating the acquired phase states, beginning with a phase state corresponding with a least delayed input replica, for detecting a first phase state transition and when detected, for setting each acquired phase state subsequent thereto to a predefined, set phase state.

Claim 24

A transceiver circuit for a subsystem of a system wherein data is transferred along multiple channels asynchronously among a plurality of subsystems, said transceiver circuit comprising: multiple transceiver macros, each transceiver macro being coupled to a different one of the multiple channels, and comprising a receiver circuit and a transmitter circuit, each receiver circuit having a digitally implemented phase aligner for aligning an input signal with a reference clock signal for subsequent synchronous data operations within the subsystem of the plurality of subsystems; and means, coupled to each of the multiple transceiver macros, for generating the reference clock signal from one of a plurality of reference clock signals, wherein each receiver circuit of said multiple transceiver macros may receive the reference clock signal such that at least some unique reference clock signals of different frequency are provided.

Claim 25

The transceiver circuit of claim 24, wherein said digitally implemented phase aligner of each of said multiple transceiver macros comprises: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; clock adjustment means for receiving the reference clock signal and for producing therefrom a sampling clock signal having a clocking transition, said sampling clock signal having a same frequency as the reference clock signal and a phase offset from the input signal, said phase of the sampling clock signal being offset from the reference clock signal when the reference clock signal is substantially in phase with the input signal; selection means for detecting a phase relationship between said sampling clock signal and at least some of said input replicas, and for identifying based thereon one of said input replicas as closely synchronized with said sampling clock signal, said identified one of the input replicas comprising a synchronous replica; and output means for retiming and for outputting the synchronous replica as a data output signal closely synchronized with the reference clock signal, said output means for retiming the synchronous replica including means for compensating for said clock adjustment means' sampling clock signal phase offset relative to the reference clock signal when the reference clock signal is substantially in phase with the input signal.

Claim 26

The transceiver circuit of claim 24, wherein said digitally implemented phase aligner of each of said multiple transceiver macros comprises: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; means for acquiring phase states for each input replica relative to the reference clock signal, including means for evaluating the acquired phase states, beginning with a phase state corresponding with a least delayed input replica, for detecting a first phase state transition and when detected, for setting each acquired phase state subsequent thereto to a predefined, set phase state; selection means, coupled to said means for acquiring phase states, for identifying based on phase states one of the input replicas as closely synchronized with the reference clock signal, said identified one of the input replicas comprising a synchronous replica; and means for outputting the synchronous replica as a data output signal synchronized with the reference clock signal.

Claim 27

The transceiver circuit of claim 24, wherein said digitally implemented phase aligner of each of said multiple transceiver macros comprises: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; selection means, coupled to the delay circuit, for identifying one of said input replicas as closely synchronized with the reference clock signal, said identified one of the input replicas comprising a synchronous replica; and compensation means for evaluating the synchronous replica for cycle slip, and for outputting based thereon, a slip-cycle compensated data output signal whenever a cycle slip is determined, said slip-cycle compensated data output signal being closely synchronized with the reference clock signal.

Claim 28

The transceiver circuit of claim 24, wherein said digitally implemented phase aligner of each of said multiple transceiver macros comprises: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; clock adjustment means for receiving the reference clock signal and for producing therefrom a sampling clock signal having a clocking transition, said sampling clock signal having a same frequency as the reference clock signal and a phase offset from the input signal; means for acquiring phase states for the input replicas relative to the sampling clock signal, said means for acquiring phase states including means for filtering incorrect phase states; selection means, coupled to said means for acquiring phase states, for identifying based on acquired phase states one of the input replicas as closely synchronized with the sampling clock signal, said identified one of the input replicas comprising a synchronous replica; and retiming and cycle-slip compensation means for outputting a slip-cycle compensated data output signal closely synchronized with the reference clock signal, said retiming means including means for adjusting the phase of the synchronous replica when the sampling clock signal is phase offset from the reference clock signal, said phase compensating of the synchronous replica being equal to the phase offset of the sampling clock signal relative to the reference clock signal.

Claim 29

The transceiver circuit of claim 24, wherein said means for generating the reference clock signal includes a programmable frequency multiplier connected to clock each of said multiple transceiver macros, and wherein each of said multiple transceiver macros includes its own frequency divider coupled to the programmable frequency multiplier.

Claim 30

A data transfer network wherein data is transferred along multiple channels asynchronously among a plurality of subsystems, said network comprising: multiple synchronous subsystems, each synchronous subsystem having a transceiver circuit comprising (i) multiple transceiver macros, each transceiver macro being coupled to a different one of the multiple channels, and comprising a receiver circuit and a transmitter circuit, each receiver circuit having a digitally implemented phase aligner for aligning a received input signal with a reference clock signal for subsequent synchronous data operations within the subsystem of the multiple subsystems, and (ii) means, coupled to said multiple transceiver macros, for generating the reference clock signal from one of a plurality of reference clock signals, wherein each receiver circuit of said multiple transceiver macros may receive the reference clock signal such that at least some unique reference clock signals of different frequency are provided to the multiple transceiver macros; and said multiple channels coupling said plurality of subsystems.

Claim 31

The network of claim 30, wherein said digitally implemented phase aligner of each of said multiple transceiver macros comprises: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; means for acquiring phase states for each input replica relative to the reference clock signal, including means for evaluating the acquired phase states, beginning with a phase state corresponding with a least delayed input replica, for detecting a first phase state transition and when detected, for setting each acquired phase state subsequent thereto to a predefined, set phase state; selection means, coupled to said means for acquiring phase states, for identifying based on phase states one of the input replicas as closely synchronized with the reference clock signal, said identified one of the input replicas comprising a synchronous replica; and means for outputting the synchronous replica as a data output signal synchronized with the reference clock signal.

Claim 32

The network of claim 30, wherein said digitally implemented phase aligner of each of said multiple transceiver macros comprises: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; selection means, coupled to the delay circuit, for identifying one of said input replicas as closely synchronized with the reference clock signal, said identified one of the input replicas comprising a synchronous replica; and compensation means for evaluating the synchronous replica for cycle slip, and for outputting based thereon, a slip-cycle compensated data output signal whenever a cycle slip is determined, said slip-cycle compensated data output signal being closely synchronized with the reference clock signal.

Claim 33

The network of claim 30, wherein said digitally implemented phase aligner of each of said multiple transceiver macros comprises: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; clock adjustment means for receiving the reference clock signal and for producing therefrom a sampling clock signal having a clocking transition, said sampling clock signal having a same frequency as the reference clock signal and a phase offset from the input signal; means for acquiring phase states for the input replicas relative to the sampling clock signal, said means for acquiring phase states including means for filtering incorrect phase states; selection means, coupled to said means for acquiring phase states, for identifying based on acquired phase states one of the input replicas as closely synchronized with the sampling clock signal, said identified one of the input replicas comprising a synchronous replica; and retiming and cycle-slip compensation means for outputting a slip-cycle compensated data output signal closely synchronized with the reference clock signal, said retiming means including means for adjusting the phase of the synchronous replica when the sampling clock signal is phase offset from the reference clock signal, said phase compensating of the synchronous replica being equal to the phase offset of the sampling clock signal relative to the reference clock signal.

Claim 34

The network of claim 30, wherein said means for generating the reference clock signal comprising a programmable frequency multiplier connected to clock each of said multiple transceiver macros.

Claim 36

The method of claim 35, wherein said acquiring step (c) includes evaluating each acquired phase state, beginning with a phase state corresponding with a least delayed input replica, and detecting a first phase state transition and when detected, setting each acquired phase state subsequent thereto to a predefined, set phase state.

Claim 37

The method of claim 35, wherein said selecting step (e) includes selecting an input replica most closely synchronized with the reference clock signal.

Claim 38

The method of claim 35, wherein said selecting step (e) includes selecting a one of said input replicas having a phase which leads the reference clock signal.

Claim 39

The method of claim 35, further comprising the step of: evaluating the synchronous replica for cycle slip, and when identified, for outputting the data output signal as a slip-cycle compensated data output signal synchronized with the reference clock signal; saving a previous synchronous replica and wherein said slip-cycle evaluating includes identifying a phase offset between the synchronous replica and the previous synchronous replica; deleting the data output signal when the phase of the synchronous replica lags by more than 360° the phase of the previous synchronous replica, and adding an output data bit before the data output signal when the phase of the synchronous replica leads the phase of the previous synchronous replica by more than 360°.