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US5532632A
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Method and circuit for synchronizing an input data stream with a sample clock
Assignee: The AT&T MVPD Group LLC
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Filing: 1994-02-01
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Granted: 1996-07-02
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Expires: 2014-02-01
Abstract
Abstract A method and circuit for synchronizing input data with a sample clock in which, for each sample clock cycle, the position of input data transitions relative to an acceptable neutral zone is detected. The neutral zone is of predetermined time duration and is positioned in a predetermined location relative to the active edge of the clock signal. If the transition occurs during the neutral zone no corrective action is warranted. If the data transitions move beyond the neutral zone, into a predetermined time interval on either side of the active edge, this event is captured and used by control logic to effect a return of the data transitions to a location within the neutral zone.
Inventors
- 👤 Bruce C. Kent
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:31
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/0079; H04L7/0083; H04L7/0016; H04L7/0033; H04L7/0041
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
212 words
A synchronizing circuit comprising a data input means for receiving an input data stream, sample clock input means for receiving a sample clock signal of predetermined frequency establishing a predetermined sample clock period, and a data output means providing a synchronized output data stream, said circuit comprising: variable time delay means responsive to said input data stream for providing a delayed data stream having data transitions which are adjustable relative to the data transitions occurring in said input data stream; means responsive to said delayed data stream for providing said synchronized output data stream; logic means for detecting the occurrence of data transitions within a predetermined time interval on either side of the active edge of said clock signal; means for adjusting the delay interval of said variable time delay means, in response to data transitions within said predetermined time interval, to either increase or decrease said delay interval to thereby return the data transitions of said output data stream to a neutral zone outside said predetermined time interval; and wherein said logic means includes means for defining said neutral zone comprising first and second fixed delay means serially connected with said variable time delay means and first and second exclusive OR gates connected across said first and second fixed delay means.
Claim 2
Dependent Claim
212 words
A synchronizing circuit comprising a data input means for receiving an input data stream, sample clock input means for receiving a sample clock signal of predetermined frequency establishing a predetermined sample clock period, and a data output means providing a synchronized output data stream, said circuit comprising: variable time delay means responsive to said input data stream for providing a delayed data stream having data transitions which are adjustable relative to the data transitions occurring in said input data stream; means responsive to said delayed data stream for providing said synchronized output data stream; logic means for detecting the occurrence of data transitions within a predetermined time interval on either side of the active edge of said clock signal; means for adjusting the delay interval of said variable time delay means, in response to data transitions within said predetermined time interval, to either increase or decrease said delay interval to thereby return the data transitions of said output data stream to a neutral zone outside said predetermined time interval; and wherein said logic means includes means for defining said neutral zone comprising first and second fixed delay means serially connected with said variable time delay means and first and second exclusive OR gates connected across said first and second fixed delay means.
Claim 3
Dependent Claim
27 words
The circuit defined in claim 1 wherein said logic means further includes means for capturing and storing the output of said first and second exclusive OR gates.
Claim 4
Dependent Claim
43 words
The circuit defined in claim 2 wherein said adjusting means is a binary up/down counter whose counting direction is dependent on the state of said storing means and which normally sets said variable time delay means to the midpoint of its delay range.
Claim 5
Dependent Claim
97 words
The circuit defined in claim 1 wherein said adjusting means is a binary up/down counter which normally sets said variable time delay means to the midpoint of its delay range and said up/down counter being enabled to count up and thereby change said variable delay in one direction in response to detection of a data transition on one side of said neutral zone, said up/down counter being enabled to count down and thereby change said variable delay in the opposite direction in response to detection of a data transition on the other side of said neutral zone.
Claim 6
Dependent Claim
159 words
A synchronizing circuit comprising a data input terminal for connection with an input data stream, a sample clock input terminal for connection with clock means providing a sample clock signal of predetermined frequency establishing a predetermined sample clock period, and a data output terminal, said circuit comprising; programmable delay circuit means connected with said input terminal and providing a first delayed data stream of adjustable time delay relative to said input data stream, first and second fixed time delay means serially connected with the output of said programmable delay circuit means, first and second exclusive OR gate means, connected across said first and second fixed time delay means respectively, first and second storage means for capturing and storing the output of said first and second gate means in response to an active edge of said clock signal, delay control means for controlling the delay time of said programmable delay means as a function of the state of storage means.
Claim 7
Dependent Claim
159 words
A synchronizing circuit comprising a data input terminal for connection with an input data stream, a sample clock input terminal for connection with clock means providing a sample clock signal of predetermined frequency establishing a predetermined sample clock period, and a data output terminal, said circuit comprising; programmable delay circuit means connected with said input terminal and providing a first delayed data stream of adjustable time delay relative to said input data stream, first and second fixed time delay means serially connected with the output of said programmable delay circuit means, first and second exclusive OR gate means, connected across said first and second fixed time delay means respectively, first and second storage means for capturing and storing the output of said first and second gate means in response to an active edge of said clock signal, delay control means for controlling the delay time of said programmable delay means as a function of the state of storage means.
Claim 8
Dependent Claim
75 words
The invention defined in claim 5 wherein said first and second storage means assume a first binary state when transitions in said delayed output data stream occur outside a predetermined time interval extending equally on either side of the active edge of said sample clock signal, and one of said first and second storage means assumes a second binary state when a transition in said delayed output data stream occurs within said predetermined time interval.
Claim 9
Dependent Claim
50 words
The invention defined in claim 6 wherein said delay control means is an up/down counter which is enabled when either of said first and second storage means assume said second binary state and whose counting direction is dependent on which one of said storage means assumes said second binary state.
References Cited (Backward Citations)
US3851101A
Cited
US4700347A
Cited
US4841551A
Cited
US4821296A
Cited
US5022057A
Cited
US5034967A
Cited
US5022056A
Cited
US5278873A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-02 | 2000-01-01 | 2000-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-02 | 2004-01-01 | 2004-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-02 | 2008-01-01 | 2008-07-02 | $7700.00 | Window Closed / Lapsed |