US5648931A
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US
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High speed synchronous logic data latch apparatus
Assignee: Renesas Electronics Corp
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Filing: 1995-06-27
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Granted: 1997-07-15
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Expires: 2015-06-27
Abstract
Abstract In a logic data latch apparatus including a clock signal input circuit for receiving a clock signal and at least two logic signal input circuits for receiving logic signals, a logic circuit is connected to the logic signal input circuits so that a logic operation is performed upon the logic signals. An output signal of the logic circuit is latched in a latch circuit in synchronization with the clock signal.
Inventors
- 👤 Takashi Obara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:17
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; H03K3/01; H03K3/012
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
103 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; at least two logic signal input circuits for receiving logic signals; a logic circuit, connected to outputs of said logic signal input circuits, for performing a logic operation upon said logic signals; and a latch circuit, connected to said clock signal input circuit and said logic circuit, for latching an output signal of said logic circuit in synchronization with said clock signal, wherein a set up time of said logic signals with respect to said clock signal is larger than a delay time of said logic circuit.
Claim 2
Dependent Claim
103 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; at least two logic signal input circuits for receiving logic signals; a logic circuit, connected to outputs of said logic signal input circuits, for performing a logic operation upon said logic signals; and a latch circuit, connected to said clock signal input circuit and said logic circuit, for latching an output signal of said logic circuit in synchronization with said clock signal, wherein a set up time of said logic signals with respect to said clock signal is larger than a delay time of said logic circuit.
Claim 3
Dependent Claim
87 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; at least two logic signal input circuits for receiving logic signals; a logic circuit, connected to outputs of said logic signal input circuits, for performing a logic operation upon said logic signals; and a latch circuit, connected to said clock signal input circuit and said logic circuit, for latching an output signal of said logic circuit in synchronization with said clock signal; and a delay line connected to said latch circuit.
Claim 4
Dependent Claim
87 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; at least two logic signal input circuits for receiving logic signals; a logic circuit, connected to outputs of said logic signal input circuits, for performing a logic operation upon said logic signals; and a latch circuit, connected to said clock signal input circuit and said logic circuit, for latching an output signal of said logic circuit in synchronization with said clock signal; and a delay line connected to said latch circuit.
Claim 5
Dependent Claim
94 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; at least two logic signal input circuits for receiving logic signals; delay lines, each connected to one of said logic signal input circuits, for delaying said logic signals; latch circuits, each connected to one of said delay lines, for latching an output signal of a respective one of said delay lines in synchronization with said clock signal; and a logic circuit, connected to said latch circuits, for performing a logic operation upon output signals of said latch circuits.
Claim 6
Dependent Claim
94 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; at least two logic signal input circuits for receiving logic signals; delay lines, each connected to one of said logic signal input circuits, for delaying said logic signals; latch circuits, each connected to one of said delay lines, for latching an output signal of a respective one of said delay lines in synchronization with said clock signal; and a logic circuit, connected to said latch circuits, for performing a logic operation upon output signals of said latch circuits.
Claim 7
Dependent Claim
35 words
An apparatus as set forth in claim 3, wherein a set up time of said logic signals with respect to said clock signal is larger than a delay time of each of said delay lines.
Claim 8
Dependent Claim
92 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; at least two logic signal input circuits for receiving logic signals; a logic circuit, connected to said logic signal input circuits, for performing a logic operation upon said logic signals; a delay line connected to said logic circuit, for delaying an output signal of said logic circuit; a latch circuit, connected to said clock signal input circuit and said delay line, for latching an output signal of said delay line in synchronization with said clock signal.
Claim 9
Dependent Claim
92 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; at least two logic signal input circuits for receiving logic signals; a logic circuit, connected to said logic signal input circuits, for performing a logic operation upon said logic signals; a delay line connected to said logic circuit, for delaying an output signal of said logic circuit; a latch circuit, connected to said clock signal input circuit and said delay line, for latching an output signal of said delay line in synchronization with said clock signal.
Claim 10
Dependent Claim
44 words
An apparatus as set forth in claim 5, wherein a set up time of said logic signals with respect to said clock signal is larger than a sum of a delay time of said logic circuit and a delay time of said delay line.
Claim 11
Dependent Claim
88 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; at least two logic signal input circuits for receiving logic signals; delay lines, each connected to one of said logic signal input circuits, for delaying said logic signals; a logic circuit, connected to said delay lines, for performing a logic operation upon output signals of said delay lines; and a latch circuit, connected to said delay lines, for latching an output signal of said logic circuit in synchronization with said clock signal.
Claim 12
Dependent Claim
88 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; at least two logic signal input circuits for receiving logic signals; delay lines, each connected to one of said logic signal input circuits, for delaying said logic signals; a logic circuit, connected to said delay lines, for performing a logic operation upon output signals of said delay lines; and a latch circuit, connected to said delay lines, for latching an output signal of said logic circuit in synchronization with said clock signal.
Claim 13
Dependent Claim
46 words
An apparatus as set forth in claim 7 wherein a set up time of said logic signals with respect to said clock signal is larger than a sum of a delay time of each of said delay lines and a delay time of said logic circuit.
Claim 14
Dependent Claim
65 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; a logic signal input circuit for receiving a logic signal.; a delay line, connected to said logic input circuit; and a latch circuit, connected to said clock signal input circuit and said delay line, for latching an output signal of said delay line in synchronization with said clock signal.
Claim 15
Dependent Claim
65 words
A logic data latch apparatus comprising: a clock signal input circuit for receiving a clock signal; a logic signal input circuit for receiving a logic signal.; a delay line, connected to said logic input circuit; and a latch circuit, connected to said clock signal input circuit and said delay line, for latching an output signal of said delay line in synchronization with said clock signal.
Claim 16
Dependent Claim
33 words
An apparatus as set forth in claim 9, wherein a set up time of said logic signal with respect to said clock signal is larger than a delay time of said delay line.
Claim 17
Dependent Claim
124 words
A synchronous semiconductor memory device comprising: a system clock signal input circuit for receiving a system clock signal; a plurality of control signal input circuits for receiving control signals; a plurality of logic circuits, connected to outputs of said control signal input circuits, for performing logic operations upon output signals of said control signal input circuits; and a plurality of latch circuits, each connected to one of said logic circuits and to said system clock signal input circuit, for latching an output signal of a respective one of said logic circuits in synchronization with said system clock signal, wherein a set up time of said control signals with respect to said system clock signal is larger than a delay time of said logic circuits.
Claim 18
Dependent Claim
124 words
A synchronous semiconductor memory device comprising: a system clock signal input circuit for receiving a system clock signal; a plurality of control signal input circuits for receiving control signals; a plurality of logic circuits, connected to outputs of said control signal input circuits, for performing logic operations upon output signals of said control signal input circuits; and a plurality of latch circuits, each connected to one of said logic circuits and to said system clock signal input circuit, for latching an output signal of a respective one of said logic circuits in synchronization with said system clock signal, wherein a set up time of said control signals with respect to said system clock signal is larger than a delay time of said logic circuits.
Claim 19
Dependent Claim
120 words
A synchronous semiconductor memory device comprising: a system clock signal input circuit for receiving a system clock signal; a plurality of control signal input circuits for receiving control signals; a plurality of delay lines, each connected to one of said control signal input circuits, for delaying output signals of said control signal input circuits; a plurality of latch circuits, each connected to one of said delay lines and to said system clock signal input circuit, for latching an output signal of a respective one of said logic circuits in synchronization with said system clock signal; and a plurality of logic circuits, each connected to one of said latch circuits, for performing logic operations upon output signals of said latch circuits.
Claim 20
Dependent Claim
120 words
A synchronous semiconductor memory device comprising: a system clock signal input circuit for receiving a system clock signal; a plurality of control signal input circuits for receiving control signals; a plurality of delay lines, each connected to one of said control signal input circuits, for delaying output signals of said control signal input circuits; a plurality of latch circuits, each connected to one of said delay lines and to said system clock signal input circuit, for latching an output signal of a respective one of said logic circuits in synchronization with said system clock signal; and a plurality of logic circuits, each connected to one of said latch circuits, for performing logic operations upon output signals of said latch circuits.
Claim 21
Dependent Claim
36 words
A device as set forth in claim 12, wherein a set up time of said control signals with respect to said system clock signal is larger than a delay time of each of said delay lines.
Claim 22
Dependent Claim
117 words
A synchronous semiconductor memory device comprising: a system clock signal input circuit for receiving a system clock signal; a plurality of control signal input circuits for receiving control signals; a plurality of logic circuits, connected to said control signal input circuits, for performing logic operations upon output signals of said control signal input circuits; a plurality of delay lines, each connected to one of said logic circuits, for delaying output signals of said logic circuit; and a plurality of latch circuits, each connected to one of said delay lines and to said system clock signal input circuit, for latching an output signal of a respective one of said delay lines in synchronization with said system clock signal.
Claim 23
Dependent Claim
117 words
A synchronous semiconductor memory device comprising: a system clock signal input circuit for receiving a system clock signal; a plurality of control signal input circuits for receiving control signals; a plurality of logic circuits, connected to said control signal input circuits, for performing logic operations upon output signals of said control signal input circuits; a plurality of delay lines, each connected to one of said logic circuits, for delaying output signals of said logic circuit; and a plurality of latch circuits, each connected to one of said delay lines and to said system clock signal input circuit, for latching an output signal of a respective one of said delay lines in synchronization with said system clock signal.
Claim 24
Dependent Claim
49 words
A device as set forth in claim 14, wherein a set up time of said control signals with respect to said system clock signal is larger than a sum of a delay time of one of said logic circuits and a delay time of one of said delay lines.
Claim 25
Dependent Claim
116 words
A synchronous semiconductor memory device comprising: a system clock signal input circuit for receiving a system clock signal; a plurality of control signal input circuits for receiving control signals; a plurality of delay lines, each connected to one of said control signal input circuits, for delaying output signals of said control input circuit, a plurality of logic circuits, connected to said delay lines, for performing logic operations upon output signals of said delay lines; and a plurality of latch circuits, each connected to one of said logic circuits and to said system clock signal input circuit, for latching an output signal of a respective one of said logic circuits in synchronization with said system clock signal.
Claim 26
Dependent Claim
116 words
A synchronous semiconductor memory device comprising: a system clock signal input circuit for receiving a system clock signal; a plurality of control signal input circuits for receiving control signals; a plurality of delay lines, each connected to one of said control signal input circuits, for delaying output signals of said control input circuit, a plurality of logic circuits, connected to said delay lines, for performing logic operations upon output signals of said delay lines; and a plurality of latch circuits, each connected to one of said logic circuits and to said system clock signal input circuit, for latching an output signal of a respective one of said logic circuits in synchronization with said system clock signal.
Claim 27
Dependent Claim
48 words
A device as set forth in claim 16, wherein a set up time of said control signals with respect to said clock signal is larger than a sum of a delay time of one of said delay lines and a delay time of one of said logic circuits.
References Cited (Backward Citations)
US3783254A
Cited
JPH02203611A
Cited
US5295115A
Cited
EP0541840A1
Cited
EP0548894A2
Cited
EP0552046A2
Cited
US5426606A
Cited
US5444667A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-14 | 2001-01-13 | 2001-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-14 | 2005-01-13 | 2005-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-14 | 2009-01-13 | 2009-07-15 | $7700.00 | Window Closed / Lapsed |