EP0552046A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Complementary logic circuit
Assignee: Sony Corp
•
Filing: 1993-01-15
•
Granted: —
•
Expires: 2013-01-15
Abstract
Abstract There is disclosed a circuit arrangement to permit reduction of the occupation area and the power consumption in a complementary logic circuit constituting a sequence circuit such that it is used in a manner switched between ON state and OFF state. This circuit arrangement as a sequence circuit comprises a delay circuit 2 comprised of a group of D flip-flops of the dynamic type and a combination circuit 1 connected to the delay circuit, thus to allow all inputs of the combination circuit 1 to be compulsorily brought into a predetermined state during an operation stop period of the delay circuit by an input control circuit 3, and to allow the delay circuit to be placed in a data through condition, with each of master and slave latches of the group of flip-flops constituting the delay circuit being caused to be inoperative or inactive, by an operation stop control circuit 4.
Inventors
- 👤 Masato C/O Sony Corporation Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 05:53
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
127 words
A complementary logic circuit constituting a sequence circuit, comprising: delay circuit means comprised of a group of dynamic delay type flip-flops; combination circuit means connected to said delay circuit means; input control means connected to the input side of said combination circuit means, and adapted for allowing all inputs of said combination circuit to be compulsorily placed at a predetermined logic level during an operation stop period of said delay circuit means; and operation stop control means connected to said delay circuit means, and adapted for allowing each of master and slave latches of said dynamic delay type flip-flops constituting said delay circuit means to be inoperative or inactive so that said delay circuit means is brought into a data through condition for the operation stop period.
Claim 2
Dependent Claim
55 words
A complementary logic circuit as set forth in claim 1, wherein said operation stop control means generates first and second clocks to be supplied to allow inputs of dynamic delay type flip-flops to be brought into an enable state, and to allow these clocks to be place at high level during the operation stop period.
Claim 3
Dependent Claim
35 words
A complementary logic circuit as set forth in claim 2, wherein said operation stop period is dependent upon a stop control signal supplied to said input control means and said operation stop control means, simultaneously.
Claim 4
Dependent Claim
57 words
A complementary logic circuit as set forth in claim 3, wherein said input control means includes first AND gate means of which output terminal is connected to one input terminal of said combination circuit means, input data and the stop control signal being adapted to be supplied to input terminals of said first AND gate means, respectively.
Claim 5
Dependent Claim
62 words
A complementary logic circuit as set forth in claim 4, wherein said input control means further comprises second AND gate means connected between said combination circuit means and said delay circuit means, output data from said combination circuit means to be supplied to said delay circuit means being controlled by supplying the operation stop control signal to said second AND gate means.
Claim 6
Dependent Claim
112 words
A complementary logic circuit comprising: delay circuit means comprised of a group of dynamic delay type flip-flops; input control means connected to the input side of said delay circuit means, and for allowing an input of said delay circuit means to be compulsorily placed at a predetermined logic level during an operation stop state of said delay circuit means; and operation stop control means connected to said delay circuit means, and for allowing each of master and slave latches of said group of flip-flops constituting said delay circuit means to be inoperative or inactive so that said delay circuit means is brought into a data through condition during the operation stop period.
Claim 7
Dependent Claim
59 words
A complementary logic circuit as set forth in claim 6, wherein said operation stop control means generates first and second clocks to be supplied to allow an input of said delay circuit means to be brought into an enable state, and to cause said first and second clocks to be placed at high level during the operation stop period.
Claim 8
Dependent Claim
80 words
A complementary logic circuit as set forth in claim 7, wherein said input control means includes AND gate means of which output terminal is connected to the input side of said delay circuit means, input data and stop control signal being adapted to be supplied to input terminals of said AND gate means, the operation stop period being adapted to depend upon said stop control signal supplied to each of said input control means and said operation stop control means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.