US6026219A — Behavioral synthesis links to logic synthesis

Claim 1

Independent Claim 104 words

A method performed by a data processing system having a memory comprising the steps of: synthesizing a representation of a digital circuit in said memory; identifying an operation in said representation of said digital circuit; scheduling said operation within a clock cycle if an execution time of said operation is less than a time period for one clock cycle; and generating a multicycle constraint value for said operation if said execution time of said operation is more than said time period for one clock cycle, wherein said multicycle constraint value indicates said operation requires N cycles to execute and N is two or more.

Claim 2

Independent Claim 104 words

A method performed by a data processing system having a memory comprising the steps of: synthesizing a representation of a digital circuit in said memory; identifying an operation in said representation of said digital circuit; scheduling said operation within a clock cycle if an execution time of said operation is less than a time period for one clock cycle; and generating a multicycle constraint value for said operation if said execution time of said operation is more than said time period for one clock cycle, wherein said multicycle constraint value indicates said operation requires N cycles to execute and N is two or more.

Claim 3

Dependent Claim 30 words

The method of claim 1, further comprising the step of measuring in units of time smaller than said time period for one clock cycle, an execution time of said operation.

Claim 4

Dependent Claim 76 words

The method of claim 1, wherein the step of creating said multicycle constraint value further includes the steps of: identifying, in said representation of said digital circuit, a first register driving said multicycle operation; identifying, in said representation of said digital circuit, a second register driven by said multicycle operation; and annotating, in said representation of said digital circuit in the memory, a path between said first register and said second register as requiring N cycles.

Claim 5

Dependent Claim 23 words

The method of claim 2, further comprising the step of optimizing a technology mapping of said digital circuit according to said multicycle constraint.

Claim 6

Independent Claim 75 words

A method performed by a data processing system having a memory, comprising the steps of: translating an input representation of a digital circuit in memory into a first representation comprising a first level and a second level, wherein the first level is a higher-level representation of the digital circuit than the second level; determining delay values for the first level by timing the second level; and scheduling the first level according to the delay values.

Claim 7

Independent Claim 75 words

A method performed by a data processing system having a memory, comprising the steps of: translating an input representation of a digital circuit in memory into a first representation comprising a first level and a second level, wherein the first level is a higher-level representation of the digital circuit than the second level; determining delay values for the first level by timing the second level; and scheduling the first level according to the delay values.

Claim 8

Dependent Claim 13 words

The method of claim 5, wherein the second level is a bit-level representation.

Claim 9

Dependent Claim 19 words

The method of claim 5, wherein the step of determining further comprises technology specific timing of the second level.

Claim 10

Dependent Claim 46 words

The method of claim 5, wherein the first level is comprised of a first and a second operation, each of which is represented by a plurality of elements at the second level, and wherein the first and second operations are scheduled in the step of scheduling.

Claim 11

Dependent Claim 34 words

The method of claim 5, wherein the step of determining comprises annotating a first table, uniquely associated with a first operation of the first level, with a first ready time of the first operation.

Claim 12

Dependent Claim 34 words

The method of claim 9, wherein the step of determining comprises setting the arrival time of an input of the second level, corresponding to an input of the first operation, to a predetermined value.

Claim 13

Dependent Claim 13 words

The method of claim 10, wherein the first table is a chaining table.

Claim 14

Dependent Claim 13 words

The method of claim 9, wherein the first table is a chaining table.

Claim 15

Dependent Claim 41 words

The method of claim 9, wherein the step of determining comprises: identifying a second operation of the first level in a transitive fanout of the first operation; and annotating the first table with a second ready time of the second operation.

Claim 16

Dependent Claim 13 words

The method of claim 13, wherein the first table is a chaining table.

Claim 17

Dependent Claim 56 words

The method of claim 9, wherein the step of determining comprises: identifying an activation condition, in a transitive fanout of the first operation, wherein the activation condition can cause a second operation to be activated; determining a second chained ready time of the second operation; and annotating the first table with the second chained ready time.

Claim 18

Dependent Claim 13 words

The method of claim 15, wherein the first table is a chaining table.

Claim 19

Dependent Claim 61 words

The method of claim 15, wherein the step of determining the second chained ready time comprises the steps of: setting a second arrival time of a second input of the second operation to a predetermined value; timing the second level to produce the second chained ready time; and annotating an output of the second operation with the second chained ready time.

Claim 20

Dependent Claim 50 words

The method of claim 15, wherein the step of determining the second chained ready time comprises the steps of: getting a second ready time of the second operation from a second table uniquely associated with the second operation; and adding the second ready time to the first operation ready time.

Claim 21

Independent Claim 105 words

A system for building a digital circuit representation, the system having a processor coupled to a memory unit, said system comprising: a circuit configured to parse a text description of a digital circuit into a parsed text description: a circuit configured to translate the parsed text description into a first representation comprising a first level and a second level, wherein the first level is a higher-level representation of the digital circuit than the second level; a circuit configured to determine delay values for the first level by timing the second level; and a circuit configured to schedule the first level according to the delay values.

Claim 22

Independent Claim 105 words

A system for building a digital circuit representation, the system having a processor coupled to a memory unit, said system comprising: a circuit configured to parse a text description of a digital circuit into a parsed text description: a circuit configured to translate the parsed text description into a first representation comprising a first level and a second level, wherein the first level is a higher-level representation of the digital circuit than the second level; a circuit configured to determine delay values for the first level by timing the second level; and a circuit configured to schedule the first level according to the delay values.

Claim 23

Dependent Claim 34 words

The system of claim 19, wherein the circuit configured to determine annotates a first table, uniquely associated with a first operation of the first level, with a first ready time of the first operation.

Claim 24

Dependent Claim 13 words

The system of claim 20, wherein the first table is a chaining table.

Claim 25

Dependent Claim 13 words

The system of claim 19, wherein the second level is a bit-level representation.

Claim 26

Dependent Claim 22 words

The system of claim 19, wherein the circuit configured to determine further comprises circuitry for technology specific timing of the second level.

Claim 27

Dependent Claim 45 words

The system of claim 19, wherein the first level is comprised of a first and a second operation, each of which is represented by a plurality of elements at the second level, and wherein the first and second operations are scheduled by the scheduling circuitry.

Claim 28

Dependent Claim 39 words

The system of claim 20, wherein the circuit configured to determine comprises arrival time circuitry for setting the arrival time of an input of the second level, corresponding to an input of the first operation, to a predetermined value.

Claim 29

Dependent Claim 51 words

The system of claim 20, wherein the circuit configured to determine comprises: a circuit configured to identify a second operation of the first level in a transitive fanout of the first operation; and a circuit configured to annotate the first chaining table with a second ready time of the second operation.

Claim 30

Dependent Claim 13 words

The system of claim 26, wherein the first table is a chaining table.

Claim 31

Dependent Claim 71 words

The system of claim 20, wherein the circuit configured to determine comprises: a circuit configured to identify an activation condition, in a transitive fanout of the first operation, the activation condition causing a second operation of the first level to be activated; a circuit configured to determine a second chained ready time of the second operation; and a circuit configured to annotate the first table with the second chained ready time.

Claim 32

Dependent Claim 71 words

The system of claim 28, wherein the circuit configured to determine the second chained ready time comprises: a circuit configured to set a second arrival time of a second input of the second operation to a predetermined value; a circuit configured to time the second representation to produce the second chained ready time; and a circuit configured to annotate an output of the second operation with the second chained ready time.

Claim 33

Dependent Claim 56 words

The system of claim 28, wherein the circuit configured to determine a second chained ready time comprises: a circuit configured to get a second ready time of the second operation from a second table uniquely associated with the second operation; and a circuit configured to add the second ready time to the first operation ready time.

Claim 34

Dependent Claim 13 words

The system of claim 28, wherein the first table is a chaining table.

Claim 35

Dependent Claim 13 words

The system of claim 25, wherein the first table is a chaining table.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2003-02-14	2003-08-16	2004-02-15	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2007-02-14	2007-08-16	2008-02-15	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2011-02-14	2011-08-16	2012-02-15	$7700.00	Window Closed / Lapsed

Behavioral synthesis links to logic synthesis

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