Procedure for incorporating timing parameters in the synthesis of logic circuit designs

Claim 3

The method of claim 1, wherein the first terminal of at least one of the selected circuit locations has, relative to various points in the circuit representation, a plurality of calculated forward timing delays, a plurality of derived budget timing delay constants, and a plurality of timing debts each calculated by subtracting one of the derived budget timing delay constants of the first terminal from a corresponding one of the forward timing delays of the first terminal, and wherein the method further comprises the step of selecting one of the timing debts of the first terminal as the timing debt to be used in determining whether the circuit representation should be modified.

Claim 4

The method of claim 2, wherein a plurality of timing data groups including at least one of said forward timing delays, said derived budget timing delay constants, and said timing debts is associated with at least one selected circuit location of the circuit representation, the method further including the step of associating each of said plurality of timing groups with a circuit location interconnection path of the circuit representation.

Claim 5

The method of claim 3, wherein the circuit representation further comprises latch components, each having at least one of the input terminals and at least one of the output terminals.

Claim 6

The method of claim 3, wherein each of the plurality of timing data groups associated with each selected circuit location further comprises time delay information for a clocked latch component.

Claim 7

The method of claim 2, wherein the circuit representation further comprises latch components each having at least one of the input terminals and at least one of the output terminals and wherein each latch component has a plurality of calculated forward timing delays, the method further comprising the step of selecting the longest forward timing delay for the latch component as the forward timing delay to be used in the calculation of the timing debt for at least one of the terminals of the latch component.

Claim 8

The method of claim 1, further comprising the step of replacing at least one selected model instance of the circuit representation stored in the memory with a different model instance in response to the calculation of at least one of the timing debts.

Claim 9

The method of claim 1, wherein the interconnected circuit locations can be traversed in any direction.

Claim 10

In a data processing system having a memory, a method of designing a circuit to be fabricated, the method comprising the steps, performed by the data processing system, of: generating, by the data processing system, a circuit representation corresponding to the circuit to be fabricated and storing the circuit representation in the memory, the circuit representation including a plurality of main input terminals, a plurality of main output terminals, a plurality of start references each having at least one point, and a plurality of interconnected model instances each having at least one input terminal and at least one output terminal; storing, by the data processing system, in the memory of the data processing system, timing information related to the circuit representation, the timing information including, for at least one input terminal and at least one output terminal of each of the plurality of model instances of the circuit representation, at least one predetermined model instance delay value representing a timing delay within the model instance and at least one predetermined media delay value representing a timing delay between terminals of different ones of the model instances of the circuit representation; calculating, by the data processing system, forward timing delays for a first one of the terminals of each model instance, each of the forward timing delays including the model instance and media delay values located between a respective one of the points in a given one of the start references and the first terminal of the model instance, wherein each forward timing delay represents a time required for a signal to travel between the respective one of the points in the given start reference and the first terminal of the model instance; assigning, by the data processing system, for each main output terminal of the circuit representation, a budget timing delay value representing a maximum acceptable time delay for a signal travelling from any of the main input terminals to the main output terminal; calculating, by the data processing system, derived budget timing delay constants for the first terminal of each model instance, each derived budget timing delay constant being calculated by subtracting each model instance and media value between one of the main output terminals and the first terminal of the model instance from the budget timing delay value assigned to the main output terminal; calculating, by the data processing system, timing debts for the first terminal of each model instance, each timing debt being calculated by subtracting one of the derived budget timing delay constants of the first terminal of the model instance from a corresponding one of the forward timing delays of the first terminal of the model instance; selecting, by the data processing system, one of the timing debts of the first terminal; determining, by the data processing system, whether the circuit representation should be modified based on a value of at least the selected timing debt; and modifying, by the data processing system, the circuit representation stored in the memory in accordance with the value of at least the selected timing debt when the determining step determines from the value of at least the selected timing debt that the circuit representation should be modified.

Claim 11

In a data processing system having a memory, a method of designing a circuit to be fabricated, the method comprising the steps, performed by the data processing system, of: generating, by the data processing system, a circuit representation corresponding to the circuit to be fabricated and storing the circuit representation in the memory, the circuit representation including a plurality of main input terminals, a plurality of main output terminals, a plurality of start references each having at least one point, and a plurality of interconnected model instances each having at least one input terminal and at least one output terminal; storing, by the data processing system, in the memory of the data processing system, timing information related to the circuit representation, the timing information including, for at least one input terminal and at least one output terminal of each of the plurality of model instances of the circuit representation, at least one predetermined model instance delay value representing a timing delay within the model instance and at least one predetermined media delay value representing a timing delay between terminals of different ones of the model instances of the circuit representation; calculating, by the data processing system, forward timing delays for a first one of the terminals of each model instance, each of the forward timing delays including the model instance and media delay values located between a respective one of the points in a given one of the start references and the first terminal of the model instance, wherein each forward timing delay represents a time required for a signal to travel between the respective one of the points in the given start reference and the first terminal of the model instance; assigning, by the data processing system, for each main output terminal of the circuit representation, a budget timing delay value representing a maximum acceptable time delay for a signal travelling from any of the main input terminals to the main output terminal; calculating, by the data processing system, derived budget timing delay constants for the first terminal of each model instance, each derived budget timing delay constant being calculated by subtracting each model instance and media value between one of the main output terminals and the first terminal of the model instance from the budget timing delay value assigned to the main output terminal; calculating, by the data processing system, timing debts for the first terminal of each model instance, each timing debt being calculated by subtracting one of the derived budget timing delay constants of the first terminal of the model instance from a corresponding one of the forward timing delays of the first terminal of the model instance; selecting, by the data processing system, one of the timing debts of the first terminal; determining, by the data processing system, whether the circuit representation should be modified based on a value of at least the selected timing debt; and modifying, by the data processing system, the circuit representation stored in the memory in accordance with the value of at least the selected timing debt when the determining step determines from the value of at least the selected timing debt that the circuit representation should be modified.

Claim 12

The method according to claim 9, wherein one of the points in the given start reference corresponds to one of the main input terminals.

Claim 13

The method according to claim 9, wherein at least one of the model instances includes a first clocked latch component activated by a first clock signal and a second clocked latch component activated by a second clock signal.

Claim 14

The method according to claim 9, wherein the interconnected model instances can be traversed in any direction.

Claim 15

The method according to claim 9, wherein the corresponding forward timing delays and derived budget timing delay constants are arranged in groups such that the forward timing delays and derived budget timing delay constants in each group relate to the same start reference.

Claim 16

The method according to claim 9, wherein: the main output terminals constitute an end reference; the main input terminals constitute a first one of the start references; a second one of the start references consists of a group of latches which are clocked by a first clock signal; and a third one of the start references consists of a group of latches which are clocked by a second clock signal.

Claim 17

In a data processing system having a memory, a method of designing a circuit to be fabricated, the method comprising the steps, performed by the data processing system, of: generating, by the data processing system, a circuit representation corresponding to the circuit to be fabricated and storing the circuit representation in the memory, the circuit representation including a main input terminal, a main output terminal, and a plurality of interconnected model instances each having at least one input terminal and at least one output terminal; storing, by the data processing system, in the memory of the data processing system, timing information related to the circuit representation, the timing information including, for at least one input terminal and at least one output terminal of each of the plurality of model instances of the circuit representation, at least one predetermined model instance delay value representing a timing delay within the model instance and at least one predetermined media delay value representing a timing delay between terminals of different ones of the model instances of the circuit representation; calculating, by the data processing system, for a first one of the terminals of each model instance, a forward timing delay including each model instance and media delay value located between the first terminal of the model instance and the main input terminal, wherein the forward timing delay represents a time required for a signal to travel between the main input terminal of the circuit representation and the first terminal of the model instance; assigning, by the data processing system, for the main output terminal of the circuit representation, a budget timing delay value representing a maximum acceptable time delay for a signal travelling from the main input terminal to the main output terminal; calculating, by the data processing system, for the first terminal of each model instance, a derived budget timing delay constant by subtracting each model instance and media value between the first terminal of the model instance and the main output terminal from the budget timing delay value; calculating, by the data processing system, for the first terminal of each model instance, a timing debt by subtracting the derived budget timing delay constant of the first terminal of the model instance from the forward timing delay of the first terminal; determining, by the data processing system, whether the circuit representation should be modified based upon a value of at least one of the calculated timing debts; and modifying, by the data processing system, the circuit representation stored in the memory in accordance with the value of at least one of the calculated timing debts when the determining step determines from the value of at least one of the calculated timing debts that the circuit representation should be modified.

Claim 18

In a data processing system having a memory, a method of designing a circuit to be fabricated, the method comprising the steps, performed by the data processing system, of: generating, by the data processing system, a circuit representation corresponding to the circuit to be fabricated and storing the circuit representation in the memory, the circuit representation including a main input terminal, a main output terminal, and a plurality of interconnected model instances each having at least one input terminal and at least one output terminal; storing, by the data processing system, in the memory of the data processing system, timing information related to the circuit representation, the timing information including, for at least one input terminal and at least one output terminal of each of the plurality of model instances of the circuit representation, at least one predetermined model instance delay value representing a timing delay within the model instance and at least one predetermined media delay value representing a timing delay between terminals of different ones of the model instances of the circuit representation; calculating, by the data processing system, for a first one of the terminals of each model instance, a forward timing delay including each model instance and media delay value located between the first terminal of the model instance and the main input terminal, wherein the forward timing delay represents a time required for a signal to travel between the main input terminal of the circuit representation and the first terminal of the model instance; assigning, by the data processing system, for the main output terminal of the circuit representation, a budget timing delay value representing a maximum acceptable time delay for a signal travelling from the main input terminal to the main output terminal; calculating, by the data processing system, for the first terminal of each model instance, a derived budget timing delay constant by subtracting each model instance and media value between the first terminal of the model instance and the main output terminal from the budget timing delay value; calculating, by the data processing system, for the first terminal of each model instance, a timing debt by subtracting the derived budget timing delay constant of the first terminal of the model instance from the forward timing delay of the first terminal; determining, by the data processing system, whether the circuit representation should be modified based upon a value of at least one of the calculated timing debts; and modifying, by the data processing system, the circuit representation stored in the memory in accordance with the value of at least one of the calculated timing debts when the determining step determines from the value of at least one of the calculated timing debts that the circuit representation should be modified.

Claim 19

The method according to claim 15, wherein the modifying step is performed automatically by the data processing system.

Claim 20

The method according to claim 15, further comprising the step of fabricating the circuit represented by the modified circuit representation.