Logic compiler for design of circuit models

Claim 1

In an electronic apparatus which generates a circuit model representative of a circuit selectable by a user, an improvement comprising: a display; means for controlling said display to present a series of displays in menu format, wherein a circuit model representative of a circuit selectable by a user is generated in response to input requests from said series of displays; behavior model generation means for generating a mathematical behavior model corresponding to said circuit selectable by said user; pattern file generating means for generating a test pattern for input into a generated circuit model and a corresponding mathematical behavior model generated by said behavior model generation means; simulation means for operating said generated circuit model and said corresponding mathematical behavior model upon said test pattern and storing outputs from said generated circuit model and said corresponding mathematical behavior model; and comparison means for comparing said outputs from said generated circuit model and said corresponding mathematical behavior model and identifying corresponding outputs which do not represent a same output.

Claim 7

A method of verifying a logic compiling system using a digital processor comprising the steps of: generating a circuit model capable of being created by said logic compiling system, said circuit model identifying logical relationships between input signals into said circuit model and output signals from said circuit model; generating a behavior model corresponding to said circuit model, said behavior model being a mathematical model of the actual circuit intended to be modelled by said circuit model; generating a pattern file consisting of one or more test vectors for application to said circuit model and said behavior model; applying each of said test vectors to said circuit model and said behavior model and obtaining output signals from said circuit model and said behavior model associated with each of said test vectors; comparing output signals from said circuit model with output signals from said behavior model and identifying output signals from said circuit model and corresponding behavior model which do not represent a same output; and repeating the above steps for other circuit model capable of being generated by said logic compiling system for which verification is desired, said above steps being carried out by said digital processor.

Claim 8

A method of verifying a logic compiling system using a digital processor comprising the steps of: generating a circuit model capable of being created by said logic compiling system, said circuit model identifying logical relationships between input signals into said circuit model and output signals from said circuit model; generating a behavior model corresponding to said circuit model, said behavior model being a mathematical model of the actual circuit intended to be modelled by said circuit model; generating a pattern file consisting of one or more test vectors for application to said circuit model and said behavior model; applying each of said test vectors to said circuit model and said behavior model and obtaining output signals from said circuit model and said behavior model associated with each of said test vectors; comparing output signals from said circuit model with output signals from said behavior model and identifying output signals from said circuit model and corresponding behavior model which do not represent a same output; and repeating the above steps for other circuit model capable of being generated by said logic compiling system for which verification is desired, said above steps being carried out by said digital processor.