Patent US6015743A successfully refreshed from Google Patents.
← Back to Patent Explorer
US6015743A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon and a hemispherical grain polysilicon layer produced according to the method

Assignee: Individual
•
Filing: 1998-04-22
•
Granted: 2000-01-18
•
Expires: 2018-04-22
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate includes, a) providing a layer of conductively doped silicon over the substrate to a thickness greater than about 200 Angstroms; b) depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; c) positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; d) with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; e) with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; f) with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 200 mTorr; and g) annealing the substrate having the deposited non-polycrystalline silicon layer in the presence of a conductivity enhancing impurity gas at an annealing temperature of from about 350° C. to about 600° C. and at an annealing pressure of from about 10 -4 Torr to about 80 Torr to in situ both diffuse conductivity enhancing impurity into the non-polycrystalline silicon layer and transform the non-polycrystalline silicon layer into a conductively doped hemispherical grain polysilicon layer.

Inventors

  • 👤 John K. Zahurak
  • 👤 Klaus F. Schuegraf
  • 👤 Randhir P.S. Thakur

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 14:57
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; Y; Y10; Y10S; Y10S148/00; Y10S148/138

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 79 words
A method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate comprising the following steps: depositing a layer of non-polycrystalline silicon over the substrate; and annealing the substrate having the deposited non-polycrystalline silicon layer within a chemical vapor deposition reactor in the presence of a conductivity enhancing impurity gas under conditions effective to in situ both diffuse conductivity enhancing impurity into the layer and transform the silicon into a conductively doped hemispherical grain polysilicon layer.
Claim 2
Independent Claim 79 words
A method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate comprising the following steps: depositing a layer of non-polycrystalline silicon over the substrate; and annealing the substrate having the deposited non-polycrystalline silicon layer within a chemical vapor deposition reactor in the presence of a conductivity enhancing impurity gas under conditions effective to in situ both diffuse conductivity enhancing impurity into the layer and transform the silicon into a conductively doped hemispherical grain polysilicon layer.
Claim 3
Dependent Claim 22 words
The semiconductor processing method of claim 1 wherein the depositing and annealing steps are conducted in the same chemical vapor deposition reactor.
Claim 4
Dependent Claim 21 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a temperature of at least about 350° C.
Claim 5
Dependent Claim 23 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a temperature from about 350° C. to about 600° C.
Claim 6
Dependent Claim 23 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a temperature from about 550° C. to about 600° C.
Claim 7
Dependent Claim 24 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a pressure from about 10 -4 Torr to about 80 Torr.
Claim 8
Dependent Claim 38 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a pressure from about 10 -4 Torr to about 80 Torr, and the effective annealing conditions comprise a temperature of at least about 350° C.
Claim 9
Dependent Claim 40 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a pressure from about 10 -4 Torr to about 80 Torr, and the effective annealing conditions comprise a temperature from about 550° C. to about 600° C.
Claim 10
Dependent Claim 83 words
The semiconductor processing method of claim 1 further comprising the following steps conducted sequentially between the depositing and annealing steps within the chemical vapor deposition reactor with the substrate positioned therein: lowering pressure within the chemical vapor deposition reactor to a first pressure; raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; and ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure.
Claim 11
Dependent Claim 21 words
The semiconductor processing method of claim 9 wherein the first and second pressures are each at or below about 200 mTorr.
Claim 12
Dependent Claim 116 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a pressure from about 10 -4 Torr to about 80 Torr, the effective annealing conditions comprise a temperature from about 550° C. to about 600° C.; and further comprising the following steps conducted sequentially between the depositing and annealing steps within the chemical vapor deposition reactor with the substrate positioned therein: lowering pressure within the chemical vapor deposition reactor to a first pressure; raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; and ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure.
Claim 13
Dependent Claim 21 words
The semiconductor processing method of claim 1 wherein the non-polycrystalline silicon layer as deposited is completely without conductivity enhancing impurity dopant.
Claim 14
Dependent Claim 183 words
A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate comprising the following steps: providing a layer of conductively doped silicon over the substrate; depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer; positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 200 mTorr; and annealing the substrate having the deposited non-polycrystalline silicon layer in the presence of a conductivity enhancing impurity gas at an annealing temperature of from about 350° C. to about 600° C. and at an annealing pressure of from about 10 -4 Torr to about 80 Torr.
Claim 15
Dependent Claim 183 words
A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate comprising the following steps: providing a layer of conductively doped silicon over the substrate; depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer; positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 200 mTorr; and annealing the substrate having the deposited non-polycrystalline silicon layer in the presence of a conductivity enhancing impurity gas at an annealing temperature of from about 350° C. to about 600° C. and at an annealing pressure of from about 10 -4 Torr to about 80 Torr.
Claim 16
Dependent Claim 22 words
The semiconductor processing method of claim 13 wherein the doped silicon layer comprises polycrystalline silicon both before and after the annealing step.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-01-17 2003-07-19 2004-01-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-01-17 2007-07-19 2008-01-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-01-17 2011-07-19 2012-01-18 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag