Patent US6004839A successfully refreshed from Google Patents.
US6004839A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with conductive plugs
Assignee: Renesas Electronics Corp
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Filing: 1997-02-20
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Granted: 1999-12-21
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Expires: 2017-02-20
Abstract
Abstract In a method of manufacturing a semiconductor device, a CMOS section composed of an N-channel MOS transistor and a P-channel MOS transistor and a memory section composed of at least a transfer gate MOS transistor is formed on a substrate. A plurality of conductive plugs is formed to penetrate a laminate insulating film to the MOS transistors. The laminate insulating film is composed of a first insulating film and a second insulating film. A capacitor section is formed on the laminate insulating film and the capacitor section is composed of an upper electrode, a dielectric film and a lower electrode. A third insulating film is formed on the laminate insulating film and the capacitor section. A wiring pattern is formed on the third insulating film to partially penetrate the second insulating film connect to the plurality of conductive plugs. A wiring pattern may be disposed in the laminate insulating film to connect at least two of the plurality of conductive plugs.
Inventors
- 👤 Yoshihiro Hayashi
- 👤 Nobuhiro Tanabe
- 👤 Tsuneo Takeuchi
- 👤 Shinobu Saito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:40
CPC Classifications
H; H10; H10B; H10B53/00; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B53/30; H10W; H10W20/00; H10W20/01
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
161 words
A method of manufacturing a semiconductor device comprising the steps of: forming on a substrate a CMOS section comprising an N-channel MOS transistor and a P-channel MOS transistor and a memory section comprising at least a transfer gate MOS transistor; forming a plurality of conductive plugs to penetrate a laminate insulating film, at least one of said plurality of conductive plugs being associated with, and connected to, one each of said MOS transistors in said CMOS section and said memory section, said laminate insulating film being comprised of a first insulating film and a second insulating film; forming a capacitor section on said laminate insulating film, said capacitor section being comprised of an upper electrode, a dielectric film and a lower electrode; forming a third insulating film on said laminate insulating film and said capacitor section; and forming a wiring pattern on said third insulating film to partially penetrate said second insulating film and connect to said plurality of conductive plugs.
Claim 2
Independent Claim
161 words
A method of manufacturing a semiconductor device comprising the steps of: forming on a substrate a CMOS section comprising an N-channel MOS transistor and a P-channel MOS transistor and a memory section comprising at least a transfer gate MOS transistor; forming a plurality of conductive plugs to penetrate a laminate insulating film, at least one of said plurality of conductive plugs being associated with, and connected to, one each of said MOS transistors in said CMOS section and said memory section, said laminate insulating film being comprised of a first insulating film and a second insulating film; forming a capacitor section on said laminate insulating film, said capacitor section being comprised of an upper electrode, a dielectric film and a lower electrode; forming a third insulating film on said laminate insulating film and said capacitor section; and forming a wiring pattern on said third insulating film to partially penetrate said second insulating film and connect to said plurality of conductive plugs.
Claim 3
Dependent Claim
68 words
A method according to claim 1, wherein said step of forming a plurality of conductive plugs includes: forming said first insulating film on said substrate, said CMOS section and said memory section; forming said second insulating film on said first insulating film; forming contact holes to penetrate said first and second insulating films to said MOS transistors; and filling said contact holes with at least one conductive material.
Claim 4
Dependent Claim
38 words
A method according to claim 2, wherein said step of filling said contact holes includes: forming a barrier film in said contact holes; and forming a heat resistant material film on said barrier film in said contact holes.
Claim 5
Dependent Claim
23 words
A method according to claim 3, wherein said step forming a barrier film includes heating said barrier film to form a silicide layer.
Claim 6
Dependent Claim
97 words
A method according to claim 1, wherein said step of forming a plurality of conductive plugs includes: forming said first insulating film on said substrate, said CMOS section and said memory section; forming first contact holes to penetrate said first insulating films to said MOS transistors; filling said first contact holes with at least one conductive material to form first contacts; forming said second insulating film on said first insulating film; forming second contact holes to penetrate said second insulating films to said first contacts; and filling said second contact holes with at least one conductive material.
Claim 7
Dependent Claim
76 words
A method according to claim 5, wherein said step of filling said first contact holes includes: forming a barrier film in said first contact holes; and filling said contact holes with a heat resistant material film on said barrier film, and wherein said step of filling said second contact holes includes: forming a barrier film in said second contact holes; and filling said second contact holes with a heat resistant material film on said first contacts.
Claim 8
Dependent Claim
66 words
A method according to claim 1, further comprising the steps of: forming said first insulating film on said substrate, said CMOS section and said memory section; forming a bit line wiring pattern on said first insulating film to penetrate said first insulating film to said transfer gate MOS transistor; and forming said second insulating film on said first insulating film to complete said laminate insulating film.
Claim 9
Dependent Claim
133 words
A method according to claim 1, further comprising the steps of: forming said first insulating film on said substrate, said CMOS section and said memory section; etching said first insulating film to form a trench pattern and to form first contact holes to said MOS transistors, a part of said first contact holes being connected to said trench pattern; filling said trench pattern and first contact holes with a film composed of conductive heat resistant material; forming said second insulating film on said first insulating film; forming second contact holes to penetrate said second insulating films to remaining ones of said first contacts which are not connected to said trench pattern; and filling said second contact holes with a film composed of conductive heat resistant material to complete said plurality of conductive plugs.
Claim 10
Dependent Claim
40 words
A method according to claim 8, wherein a part of said trench pattern which is filled said film composed of conductive heat resistant material at least one conductive material is a bit line connected to said transfer gate MOS transistor.
Claim 11
Dependent Claim
42 words
A method according to claim 1, wherein said step of forming a capacitor section includes forming a capacitor section on said laminate insulating film such that said lower electrode is positioned on and connected to one of said plurality of conductive plugs.
Claim 12
Dependent Claim
57 words
A method according to claim 1, wherein said step of forming a capacitor section includes forming said lower electrode, and wherein said step of forming said lower electrode includes: depositing first and second metal films on said laminate insulating film; and forming an oxidation resistant layer from said first metal film and crystallizing said second metal film.
Claim 13
Dependent Claim
74 words
A method according to claim 1, wherein said of forming a capacitor section includes: forming a lower electrode conductive film on said laminate insulating film; forming a dielectric film on said lower electrode conductive film; forming a protective conductive film on said dielectric film; patterning said lower electrode conductive film, said dielectric film and said protective film; forming an upper electrode conductive film; and patterning said upper electrode film to form said upper electrode.
Claim 14
Dependent Claim
44 words
A method according to claim 12, further comprising the step of depositing a hydrogen diffusion preventing conductive film, and where said patterning said upper electrode film includes patterning said hydrogen diffusion preventing conductive film at the same time as patterning said upper electrode film.
Claim 15
Dependent Claim
33 words
A method of manufacturing a semiconductor device according to claim 1, wherein each of said plurality of conductive plugs have a height substantially equal to a greatest thickness of said laminate insulating film.
Claim 16
Dependent Claim
56 words
A method of manufacturing a semiconductor device according to claim 1, wherein each of said plurality of conductive plugs have a first end closest to said substrate and a second end away from said substrate, and said second end of said conductive plugs is substantially coincident height as said top surface of said laminate insulating film.
Claim 17
Dependent Claim
25 words
A method of manufacturing a semiconductor device according to claim 1, wherein said dielectric film includes a noble metal protecting film on a ferroelectric film.
Claim 18
Dependent Claim
27 words
A method of manufacturing a semiconductor device according to claim 4, wherein said dielectric film is covered on an upper surface by a noble metal protecting film.
Claim 19
Dependent Claim
56 words
A method of manufacturing a semiconductor device according to claim 4, wherein each of said plurality of conductive plugs have a first end closest to said substrate and a second end away from said substrate, and said second end of said conductive plugs is substantially coincident height as said top surface of said laminate insulating film.
Claim 20
Dependent Claim
39 words
A method of manufacturing a semiconductor device according to claim 1, wherein each of said plurality of first conductive plugs comprises: a barrier film composed of a titanium silicide layer and a titanium nitride layer and a tungsten film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-20 | 2003-06-21 | 2003-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-20 | 2007-06-21 | 2007-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-20 | 2011-06-21 | 2011-12-21 | $7700.00 | Window Closed / Lapsed |