US5616959A
Expired / Lapsed
US
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Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators
Assignee: Texas Instruments Inc
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Filing: 1995-06-07
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Granted: 1997-04-01
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Expires: 2015-06-07
Abstract
Abstract A multi-level interconnect structure and method. A first plurality of interconnect lines (14) is located on an insulator layer (12) of semiconductor body (10). A first layer of low dielectric constant material (20), such as an organic polymer, fills an area between the first plurality of interconnect lines (14a-c) . The first layer of low dielectric constant material (20) has a height not greater than a height of the first plurality of interconnect lines (14). A first layer of silicon dioxide (18) covers the first layer of low dielectric constant material (20) and the first plurality of interconnect lines (14).
Inventors
- 👤 Shin-puu Jeng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:49
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/495; H10W20/01; H10W20/071; H10W20/074; H10W20/077; H10W20/45; H10W20/48; H10W20/098
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
128 words
A multi-level interconnect structure on a semiconductor body comprising: a. a first plurality of interconnect lines located on said semiconductor body; b. a first layer of insulating material having a dielectric constant lower than the dielectric constant of silicon dioxide filling the space between only adjacent interconnect lines of said first plurality having a distance therebetween no greater than a given distance to reduce line-to-line capacitance, said first layer of insulating material having a height not greater than a height of said first plurality of interconnect lines; and c. a first layer of silicon dioxide covering said first layer of insulating material, said first plurality of interconnect lines, and the space between adjacent interconnect lines of said first plurality having a distance therebetween greater than said given distance.
Claim 2
Dependent Claim
128 words
A multi-level interconnect structure on a semiconductor body comprising: a. a first plurality of interconnect lines located on said semiconductor body; b. a first layer of insulating material having a dielectric constant lower than the dielectric constant of silicon dioxide filling the space between only adjacent interconnect lines of said first plurality having a distance therebetween no greater than a given distance to reduce line-to-line capacitance, said first layer of insulating material having a height not greater than a height of said first plurality of interconnect lines; and c. a first layer of silicon dioxide covering said first layer of insulating material, said first plurality of interconnect lines, and the space between adjacent interconnect lines of said first plurality having a distance therebetween greater than said given distance.
Claim 3
Dependent Claim
13 words
The device of claim 1, wherein said insulating material comprises an organic polymer.
Claim 4
Dependent Claim
11 words
The device of claim 2, wherein said organic polymer comprises parylene.
Claim 5
Dependent Claim
20 words
The device of claim 1, wherein said insulating material comprises an inorganic compound having a dielectric constant less than 3.9.
Claim 6
Dependent Claim
24 words
The device of claim 1, further comprising a contact via extending through said first silicon dioxide layer to said first plurality of interconnect lines.
Claim 7
Dependent Claim
126 words
The device of claim 5, further comprising: a. a second plurality of interconnect lines located on said first silicon dioxide layer; b. a second layer of insulating material having a dielectric constant lower than the dielectric constant of silicon dioxide filling the space between only adjacent ones of said second plurality of interconnect lines having a distance therebetween no greater than said given distance, said second layer of insulating material having a height not greater than a height of said second plurality of interconnect lines; and c. a second layer of silicon dioxide covering said second layer of insulting material, said second plurality of interconnect lines, and the space between adjacent interconnect lines of said second plurality having a distance therebetween greater than said given distance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-31 | 2000-09-30 | 2001-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-31 | 2004-09-30 | 2005-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-31 | 2008-09-30 | 2009-04-01 | $7700.00 | Window Closed / Lapsed |