Process for global planarizing of surfaces for integrated semiconductor circuits

Claim 1

Process for globally planarizing surfaces of integrated circuits, which comprises: a) preparing a component with a substrate plane, and a structured layer to be planarized being disposed above the substrate plane and having a given step height for defining regions of the substrate plane covered by and regions not covered by the structured layer; b) initially producing a locally planarized silicon oxide film defining oxide trenches having a remaining silicon oxide thickness over all of the regions not covered by the structured layer being greater than the given step height after the local planarizing; c) generating photoresist structures with a photographic technique inversely to the locally planarized plane of the structured layer so that side walls of the oxide trenches are not covered by the photoresist structures; d) applying a well-adhering planarizing auxiliary layer to the photoresist structures and the silicon oxide film, the auxiliary layer being formed of a different material than the photoresist structures; e) anisotropically back-etching with substantially corresponding etch rates of the auxiliary layer and the silicon oxide and a lower etch rate of the photoresist structures until the level of the silicon oxide on the structured layers is approximately equal to the level of nonback-etched silicon oxide film under the surfaces of the photoresist structures; f) removing the photoresist; and g) removing residues of the auxiliary layer and additionally removing a damage layer produced by the anisotropic etching with an isotropic etching process.