Method for manufacturing VLSI semiconductor device

Claim 1

A method for manufacturing a VLSI semiconductor memory device comprising the steps of: doping an impurity to adjust a threshold voltage only in an active region of a cell array section of a semiconductor substrate; forming a first conductive layer serving as a gate electrode by interposing a gate oxide layer on said cell array section, and doping an n-type impurity in said active region of said cell array section to form source/drain regions, thereby forming a cell transistor; covering said cell array section in which said cell transistor is formed with an HTO layer, forming a storage node contact hole in said HTO layer, and sequentially forming a second conductive layer, an insulating layer of a capacitor, and a third conductive layer in said cell array section, thereby forming a cell capacitor; and, after the formation of said cell transistor and said cell capacitor, performing the steps of doping an impurity to adjust the threshold voltage only in an active region of a peripheral circuit section of said semiconductor substrate; forming an NMOS transistor with a lightly doped drain structure in a p-well of said peripheral circuit section, and forming a PMOS transistor with a single drain structure in an n-well of said peripheral circuit section; and covering an inter-insulating layer on the whole surface of the structure, forming a contact hole in said inter-insulating layer, and forming a metal wiring layer by a conventional method.

Claim 2

A method for manufacturing a VLSI semiconductor memory device comprising the steps of: doping an impurity to adjust a threshold voltage only in an active region of a cell array section of a semiconductor substrate; forming a first conductive layer serving as a gate electrode by interposing a gate oxide layer on said cell array section, and doping an n-type impurity in said active region of said cell array section to form source/drain regions, thereby forming a cell transistor; covering said cell array section in which said cell transistor is formed with an HTO layer, forming a storage node contact hole in said HTO layer, and sequentially forming a second conductive layer, an insulating layer of a capacitor, and a third conductive layer in said cell array section, thereby forming a cell capacitor; and, after the formation of said cell transistor and said cell capacitor, performing the steps of doping an impurity to adjust the threshold voltage only in an active region of a peripheral circuit section of said semiconductor substrate; forming an NMOS transistor with a lightly doped drain structure in a p-well of said peripheral circuit section, and forming a PMOS transistor with a single drain structure in an n-well of said peripheral circuit section; and covering an inter-insulating layer on the whole surface of the structure, forming a contact hole in said inter-insulating layer, and forming a metal wiring layer by a conventional method.