Patent US5998263A successfully refreshed from Google Patents.
US5998263A
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High-density nonvolatile memory cell
Assignee: Altera Corp
•
Filing: 1997-05-12
•
Granted: 1999-12-07
•
Expires: 2017-05-12
Abstract
Abstract A compact nonvolatile programmable memory cell. The memory cell has a floating gate (118), control gate (123), drain (108), and source regions (112). The memory cell is an electrically erasable programmable read only memory (EEPROM) cell or a Flash memory cell. Data may be stored the memory cell of the present invention for the required lifetime of the memory cell usage, and data is retained even when power is removed. The memory cell of the present invention has a substantially transverse or vertical channel (140), relative to a surface of a substrate. The memory may be used to create very high-density memory arrays.
Inventors
- 👤 Seshan Sekariapuram
- 👤 Raminda U. Madurawe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:46
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H; H10; H10B; H10B41/00; H10B41/10; H10B41/20; H10B41/23; H10B41/27; H10B41/30; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681
Claims Analysis
Total Claims: 75
Claim 1
Independent Claim
76 words
A method for fabricating a memory cell on a substrate comprising: forming parallel, alternating active regions and oxide regions in the substrate; creating a trench in the substrate transverse to the active regions and oxide regions; forming a gate oxide layer on sidewalls and a bottom of the trench; forming first polysilicon on the gate oxide along the sidewalls of the trench; and implanting n-diffusion at the bottom of the trench and in the active regions.
Claim 2
Independent Claim
76 words
A method for fabricating a memory cell on a substrate comprising: forming parallel, alternating active regions and oxide regions in the substrate; creating a trench in the substrate transverse to the active regions and oxide regions; forming a gate oxide layer on sidewalls and a bottom of the trench; forming first polysilicon on the gate oxide along the sidewalls of the trench; and implanting n-diffusion at the bottom of the trench and in the active regions.
Claim 3
Dependent Claim
22 words
The method of claim 1 further comprising: removing the first polysilicon from the sidewalls of the trench adjacent to the oxide regions.
Claim 4
Dependent Claim
24 words
The method of claim 1 further comprising: forming an insulator layer on the first polysilicon; and forming a second polysilicon on the insulator layer.
Claim 5
Dependent Claim
11 words
The method of claim 3 wherein the insulator layer is oxide-nitride-oxide.
Claim 6
Dependent Claim
33 words
The method of claim 3 wherein a first memory cell is formed on a first side of the sidewalls and a second memory cell is formed on a second side of the sidewalls.
Claim 7
Dependent Claim
15 words
The method of claim 1 wherein the first polysilicon is created using a polysilicon spacer.
Claim 8
Independent Claim
56 words
A method of fabricating a nonvolatile semiconductor memory comprising: forming a trench in a substrate; forming a first polysilicon on a sidewall of the trench; depositing a first active region beneath the trench; and forming stripes of oxide on the substrate leaving active regions between the stripes, wherein the trench is substantially perpendicular to the stripes.
Claim 9
Independent Claim
56 words
A method of fabricating a nonvolatile semiconductor memory comprising: forming a trench in a substrate; forming a first polysilicon on a sidewall of the trench; depositing a first active region beneath the trench; and forming stripes of oxide on the substrate leaving active regions between the stripes, wherein the trench is substantially perpendicular to the stripes.
Claim 10
Independent Claim
94 words
A method of producing a memory cell comprising: providing a substrate; forming a first active region in the substrate; forming a second active region at a predetermined distance above a top surface of the first active region, the second active region positioned so that a channel between the second active and first active regions is substantially transverse to a surface of the substrate; forming a floating gate substantially parallel to the channel; and forming a control gate substantially parallel to the channel, wherein the floating gate is between the control gate and the channel.
Claim 11
Independent Claim
94 words
A method of producing a memory cell comprising: providing a substrate; forming a first active region in the substrate; forming a second active region at a predetermined distance above a top surface of the first active region, the second active region positioned so that a channel between the second active and first active regions is substantially transverse to a surface of the substrate; forming a floating gate substantially parallel to the channel; and forming a control gate substantially parallel to the channel, wherein the floating gate is between the control gate and the channel.
Claim 12
Dependent Claim
14 words
The method of claim 8 wherein the source region is formed in the substrate.
Claim 13
Dependent Claim
17 words
The method of claim 8 further comprising: forming a trench in the substrate above the source region.
Claim 14
Independent Claim
79 words
A method of programming a memory cell comprising: placing a control gate at a high voltage; placing a first active region at a first potential, wherein the first active region is formed in a substrate; placing a second active region at a second potential, below the first potential, whereby electrons flow from the first active region to the second active region in a direction transverse to a surface of the substrate; and trapping hot electrons in a floating gate.
Claim 15
Independent Claim
79 words
A method of programming a memory cell comprising: placing a control gate at a high voltage; placing a first active region at a first potential, wherein the first active region is formed in a substrate; placing a second active region at a second potential, below the first potential, whereby electrons flow from the first active region to the second active region in a direction transverse to a surface of the substrate; and trapping hot electrons in a floating gate.
Claim 16
Independent Claim
93 words
A method of fabricating a semiconductor device comprising: providing a substrate having a first crystalline structure; forming a first region of the substrate having a second crystalline structure; and forming an oxide layer covering the substrate and the first region, whereby a first oxide thickness covering the first region having the second crystalline structure is different from a second oxide thickness covering a second region having the first crystalline structures, and whereby the oxide layer covering the substrate is on a different plane than that of the oxide layer covering the first region.
Claim 17
Independent Claim
93 words
A method of fabricating a semiconductor device comprising: providing a substrate having a first crystalline structure; forming a first region of the substrate having a second crystalline structure; and forming an oxide layer covering the substrate and the first region, whereby a first oxide thickness covering the first region having the second crystalline structure is different from a second oxide thickness covering a second region having the first crystalline structures, and whereby the oxide layer covering the substrate is on a different plane than that of the oxide layer covering the first region.
Claim 18
Dependent Claim
28 words
The method of fabricating a semiconductor device of claim 12 wherein the first region is a sidewall of a trench, substantially transverse to a surface of the substrate.
Claim 19
Dependent Claim
22 words
The method of fabricating a semiconductor device of claim 12 wherein the first oxide thickness is thinner than the second oxide thickness.
Claim 20
Dependent Claim
19 words
The method of fabricating a semiconductor device of claim 12 wherein the crystalline structure is <1 0 0> silicon.
Claim 21
Independent Claim
138 words
A method of fabricating a semiconductor device comprising: providing a substrate having a first crystalline structure; forming a first region of the substrate having a second crystalline structure; forming an oxide layer covering the substrate and the first region, whereby a first oxide thickness covering the first region having the second crystalline structure is different from a second oxide thickness covering a second region having the first crystalline structure; forming a first active region of the substrate; forming a second active region, located relative to the first active region so that a channel between the second active and first active regions is substantially transverse to a surface of the substrate; and forming a floating gate substantially parallel to the channel, whereby charge is transferable from the second active region through the first oxide thickness to the floating gate.
Claim 22
Independent Claim
138 words
A method of fabricating a semiconductor device comprising: providing a substrate having a first crystalline structure; forming a first region of the substrate having a second crystalline structure; forming an oxide layer covering the substrate and the first region, whereby a first oxide thickness covering the first region having the second crystalline structure is different from a second oxide thickness covering a second region having the first crystalline structure; forming a first active region of the substrate; forming a second active region, located relative to the first active region so that a channel between the second active and first active regions is substantially transverse to a surface of the substrate; and forming a floating gate substantially parallel to the channel, whereby charge is transferable from the second active region through the first oxide thickness to the floating gate.
Claim 23
Dependent Claim
27 words
The method of fabricating a semiconductor device of claim 12 wherein the first region of the substrate is a preferential charge transfer site for the semiconductor device.
Claim 24
Dependent Claim
102 words
A memory device comprising: a first active region on a substrate; a second active region, positioned relative to the first active region to permit electrons to flow between the first active region and the second active region in a direction angled relative to a surface of the substrate; a floating gate positioned in proximity to the first active region and the second active region and parallel to the flow of electrons; and an oxide layer, having a first portion between the floating gate and the second active region thinner than a second portion between the floating gate and the first active region.
Claim 25
Dependent Claim
102 words
A memory device comprising: a first active region on a substrate; a second active region, positioned relative to the first active region to permit electrons to flow between the first active region and the second active region in a direction angled relative to a surface of the substrate; a floating gate positioned in proximity to the first active region and the second active region and parallel to the flow of electrons; and an oxide layer, having a first portion between the floating gate and the second active region thinner than a second portion between the floating gate and the first active region.
Claim 26
Dependent Claim
12 words
A digital system comprising a memory cell as recited in claim 1.
Claim 27
Dependent Claim
44 words
An EEPROM memory device fabricated using a method that comprises: forming a trench in a substrate; forming a first polysilicon on a sidewall of the trench; and depositing a first active region beneath the trench, wherein the first active region underlaps the first polysilicon.
Claim 28
Dependent Claim
44 words
An EEPROM memory device fabricated using a method that comprises: forming a trench in a substrate; forming a first polysilicon on a sidewall of the trench; and depositing a first active region beneath the trench, wherein the first active region underlaps the first polysilicon.
Claim 29
Dependent Claim
44 words
A FLASH memory device fabricated using a method that comprises: forming a trench in a substrate; forming a first polysilicon on a sidewall of the trench; and depositing a first active region beneath the trench, wherein the first active region underlaps the first polysilicon.
Claim 30
Dependent Claim
44 words
A FLASH memory device fabricated using a method that comprises: forming a trench in a substrate; forming a first polysilicon on a sidewall of the trench; and depositing a first active region beneath the trench, wherein the first active region underlaps the first polysilicon.
Claim 31
Dependent Claim
50 words
A memory cell fabricated using a method that comprises: forming a trench in a substrate; forming a first polysilicon on a sidewall of the trench; and depositing a first active region beneath the trench, wherein the first active region underlaps the first polysilicon, wherein the memory cell is electrically erasable.
Claim 32
Dependent Claim
50 words
A memory cell fabricated using a method that comprises: forming a trench in a substrate; forming a first polysilicon on a sidewall of the trench; and depositing a first active region beneath the trench, wherein the first active region underlaps the first polysilicon, wherein the memory cell is electrically erasable.
Claim 33
Dependent Claim
17 words
The memory cell of claim 22, wherein an erase of the cell is achieved using Fowler-Norheim tunneling.
Claim 34
Dependent Claim
16 words
The memory cell of claim 22, wherein a program ofthe cell is achieved using Fowler-Norheim tunneling.
Claim 35
Independent Claim
86 words
A method of fabricating a nonvolatile semiconductor memory comprising: forming a trench in a substrate; forming a first polysilicon on a sidewall of the trench; forming a second polysilicon above the first polysilicon; depositing a first active region beneath the trench, wherein the first active region underlaps the first polysilicon; and depositing a second active region on a surface of the substrate in proximity to the sidewall of the trench, wherein the first polysilicon extends past the second active region along the sidewall of the trench.
Claim 36
Independent Claim
86 words
A method of fabricating a nonvolatile semiconductor memory comprising: forming a trench in a substrate; forming a first polysilicon on a sidewall of the trench; forming a second polysilicon above the first polysilicon; depositing a first active region beneath the trench, wherein the first active region underlaps the first polysilicon; and depositing a second active region on a surface of the substrate in proximity to the sidewall of the trench, wherein the first polysilicon extends past the second active region along the sidewall of the trench.
Claim 37
Dependent Claim
25 words
The method of claim 12 wherein the first and second regions are obtained by etching a trench substantially transverse to a surface of the substrate.
Claim 38
Dependent Claim
12 words
An EEPROM memory device implemented using the method recited in claim 1.
Claim 39
Dependent Claim
12 words
A FLASH memory device implemented using the method recited in claim 1.
Claim 40
Dependent Claim
18 words
A memory cell implemented using the method recited in claim 1, wherein the memory cell is electrically erasable.
Claim 41
Dependent Claim
17 words
The memory cell of claim 27, wherein an erase of the cell is achieved using Fowler-Norheim tunneling.
Claim 42
Dependent Claim
17 words
The memory cell of claim 27, wherein a program of the cell is achieved using Fowler-Norheim tunneling.
Claim 43
Dependent Claim
21 words
A plurality of memory cells fabricated using the method recited in claim 1, wherein the memory cells have separate control gates.
Claim 44
Dependent Claim
26 words
The method of claim 1 further comprising: forming a second active region on a surface of the substrate in proximity to the sidewall of the trench.
Claim 45
Dependent Claim
21 words
The method of claim 33 wherein the first polysilicon extends past the second active region along the sidewall of the trench.
Claim 46
Dependent Claim
29 words
The method of claim 1 wherein the n-diffusion at the bottom of the trench forms a second active region that is transverse to the active regions in the substrate.
Claim 47
Dependent Claim
18 words
The method of claim 1 wherein the first polysilicon is transverse to the active regions in the substrate.
Claim 48
Dependent Claim
15 words
The method of claim 3 wherein the second polysilicon is formed parallel to the trench.
Claim 49
Dependent Claim
28 words
The method of claim 1 further comprising: forming a channel parallel to each of the sidewalls of the trench and substantially transverse to a surface of the substrate.
Claim 50
Dependent Claim
16 words
The method of claim 1 further comprising: forming a source line conductor perpendicular to the trench.
Claim 51
Dependent Claim
16 words
The method of claim 1 further comprising: forming a source line conductor parallel to the trench.
Claim 52
Dependent Claim
24 words
The method of claim 40 wherein the source line conductor is coupled, at selected locations, to the n-diffusion at the bottom of the trench.
Claim 53
Dependent Claim
33 words
The method of claim 1 wherein the gate oxide layer on the sidewalls of the trench has a different thickness than that of the gate oxide layer on the bottom of the trench.
Claim 54
Dependent Claim
28 words
The method of claim 5 wherein a first control gate for the first memory cell is electrically isolated from a second control gate for the second memory cell.
Claim 55
Dependent Claim
25 words
The method of claim 1 wherein control gates for memory cells fabricated on the trench along a particular side of the sidewalls are coupled together.
Claim 56
Dependent Claim
11 words
A programmable logic device comprising the memory cell of claim 29.
Claim 57
Dependent Claim
20 words
The method of claim 7 wherein the first active region is formed perpendicular to the active regions on the substrate.
Claim 58
Dependent Claim
18 words
The method of claim 7 wherein the first polysilicon is transverse to the active regions on the substrate.
Claim 59
Dependent Claim
26 words
The method of claim 7 further comprising: forming a channel parallel to the sidewall of the trench and substantially transverse to a surface of the substrate.
Claim 60
Dependent Claim
16 words
The method of claim 7 further comprising: forming a source line conductor parallel to the trench.
Claim 61
Dependent Claim
20 words
The method of claim 49 wherein the source line conductor is coupled, at selected locations, to the first active region.
Claim 62
Dependent Claim
33 words
The method of claim 7 wherein a first memory cell is formed on a first sidewall of the trench and a second memory cell is formed on a second sidewall of the trench.
Claim 63
Dependent Claim
28 words
The method of claim 51 wherein a first control gate for the first memory cell is electrically isolated from a second control gate for the second memory cell.
Claim 64
Dependent Claim
22 words
The method of claim 51 wherein control gates for memory cells fabricated on the trench along a particular sidewall are coupled together.
Claim 65
Dependent Claim
18 words
A memory cell implemented using the method recited in claim 7, wherein the memory cell is electrically erasable.
Claim 66
Dependent Claim
11 words
A programmable logic device comprising the memory cell of claim 54.
Claim 67
Dependent Claim
18 words
The memory cell of claim 47 wherein the first polysilicon is formed parallel to the first active region.
Claim 68
Dependent Claim
19 words
The memory cell of claim 47 wherein the method further comprises: forming a second polysilicon above the first polysilicon.
Claim 69
Dependent Claim
16 words
The memory cell of claim 57 wherein the second polysilicon is formed parallel to the trench.
Claim 70
Dependent Claim
27 words
The memory cell of claim 47 further comprising: forming a channel parallel to the sidewall of the trench and substantially transverse to a surface of the substrate.
Claim 71
Dependent Claim
17 words
The memory cell of claim 47 further comprising: forming a source line conductor parallel to the trench.
Claim 72
Dependent Claim
24 words
The memory cell of claim 60 wherein the source line conductor is coupled, at selected locations, to the first active region beneath the trench.
Claim 73
Dependent Claim
30 words
The memory cell of claim 47 wherein the method further comprises: depositing a second active region on a surface of the substrate in proximity to the sidewall of the trench.
Claim 74
Dependent Claim
19 words
The memory cell of claim 62 wherein the second active region is formed perpendicular to the first active region.
Claim 75
Dependent Claim
34 words
The memory cell of claim 47 wherein a control gate for the memory cell is electrically isolated from a control gate for a second memory cell fabricated on an opposite sidewall of the trench.
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